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CS302- Digital Logic Design
LATEST SOLVED MCQS FROM FINAL TERM PAPERS
Latest Mcqs
MC100401285 [email protected] [email protected] PSMD01(IEMS)
FINALTERM EXAMINATION
Spring 2011
Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
► 1 ► 2 ► 4 ► 8 (Page 356)
Question No: 2 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by ________ and _______
► State variable, current state ► Current state, flip-flop output ► Current state and external input (Page 318) ► Input and clock signal applied
Question No: 3 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod - 6, Mod- 10 (Page 299) ► Mod-50, Mod- ► Mod-10, Mod- ► Mod-50, Mod-
Question No: 4 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
► True (Page 221) ► False
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
► Set-up time ► Hold time (Page 242) ► Pulse Interval time ► Pulse Stability time (PST)
Question No: 6 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are _______ and _________ ► ENP , ENT (Page 285) ► ENI, ENC ► ENP, ENC ► ENT, ENI
Question No: 7 ( Marks: 1 ) - Please choose one ____________ is said to occur when multiple internal variables change due to change in one input variable
► Clock Skew ► Race condition (Page 267) ► Hold delay ► Hold and Wait
Question No: 8 ( Marks: 1 ) - Please choose one The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369) ► Synchronous, asynchronous ► Preset input (PRE), Clear input (CLR) ► Clear input (CLR), Preset input (PRE)
Question No: 9 ( Marks: 1 ) - Please choose one A decade counter is __________. ► Mod-3 counter ► Mod-5 counter ► Mod-8 counter ► Mod - 10 counter (Page 274)
Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low ► It is set to logic high (Page 356) ► Remains in previous state ► State of transmission line is not used to start transmission
The three fundamental gates are ___________ ► AND, NAND, XOR ► OR, AND, NAND ► NOT, NOR, XOR ► NOT, OR, AND (Page 40)
Question No: 17 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory ► The structure of memory ► The size of decoding unit ► The size of the address bus of the microprocessor (Page 430)
Question No: 18 ( Marks: 1 ) - Please choose one Stack is an acronym for _________
► FIFO memory ► LIFO memory (Page 429) ► Flash Memory ► Bust Flash Memory
Question No: 19 ( Marks: 1 ) - Please choose one Addition of two octal numbers “36” and “71” results in ________
► 213 ► 123 ► 127 ► 345
Question No: 20 ( Marks: 1 ) - Please choose one ___________ is one of the examples of synchronous inputs. ► J-K input (Page 235) ► EN input ► Preset input (PRE) ► Clear Input (CLR)
Question No: 21 ( Marks: 1 ) - Please choose one __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
► Race condition ► Clock Skew (Page 226) ► Ripple Effect ► None of given options
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000 ► 1101 (not sure) ► 1011 ► 1111
Question No: 23 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 332) ► Current state and outputs ► Previous state and inputs ► Previous state and outputs
Question No: 24 ( Marks: 1 ) - Please choose one ________ is used to simplify the circuit that determines the next state.
► State diagram ► Next state table ► State reduction ► State assignment (Page 335)
Question No: 25 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
► 1 ► 2 ► 4 ► 8 (Page 356) rep
Question No: 26 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) ► 1100 ► 0011 ► 0000 Click here for detail ► 1111
in ____________, all the columns in the same row are either read or written.
► Sequential Access ► MOS Access ► FAST Mode Page Access (Page 413) ► None of given options
Question No: 33 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use _________
► Read Only Memory ► Fist In First Out Memory (Page 425) ► Flash Memory ► Fast Page Access Mode Memory
Question No: 34 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when ________________ ► Low - to-high transition of clock (Page 228) ► High-to-low transition of clock ► Enable input (EN) is set ► Preset input (PRE) is set
FINALTERM EXAMINATION
Spring 2010
Question No: 1 ( Marks: 1 ) - Please choose one A 8 - bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.
► 1 ► 2 ► 4 ► 8 (Page 356) rep
Question No: 2 ( Marks: 1 ) - Please choose one A frequency counter ______________
► Counts pulse width ► Counts no. of clock pulses in 1 second (Page 301) ► Counts high and low range of given clock pulse ► None of given options
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state ► Current state, flip-flop output ► Current state and external input ► Input and clock signal applied (Page 305)
Question No: 4 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod- 10 (Page 229) rep ► Mod-50, Mod- ► Mod-10, Mod- ► Mod-50, Mod-
Question No: 5 ( Marks: 1 ) - Please choose one In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.
► True (Page 221) rep ► False
Question No: 6 ( Marks: 1 ) - Please choose one Flip flops are also called _____________
► Bi-stable dualvibrators ► Bi-stable transformer ► Bi-stable multivibrators (Page 228) ► Bi-stable singlevibrators
Question No: 7 ( Marks: 1 ) - Please choose one The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
► Set-up time ► Hold time (Page 242) rep ► Pulse Interval time ► Pulse Stability time (PST)
Question No: 8 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285) ► ENI, ENC ► ENP, ENC ► ENT, ENI
In asynchronous transmission when the transmission line is idle, _________
► It is set to logic low ► It is set to logic high (Page 356) rep ► Remains in previous state ► State of transmission line is not used to start transmission
Question No: 15 ( Marks: 1 ) - Please choose one A Nibble consists of _____ bits
► 2 ► 4 (Page 394) ► 8 ► 16
Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always ________.
► A Click here for detail rep ►
Question No: 17 ( Marks: 1 ) - Please choose one Excess-8 code assigns _______ to “-8”
► 1110 ► 1100 ► 1000 ► 0000 (Page 34) rep
Question No: 18 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri (Page 446) ► Vout / Rf = - Vin / Ri ► Rf / Vin = - Ri / Vout ► Rf / Vin = Ri / Vout
LUT is acronym for ________
► Look Up Table (Page 439) rep ► Local User Terminal ► Least Upper Time Period ► None of given options
Question No: 20 ( Marks: 1 ) - Please choose one DRAM stands for __________
► Dynamic RAM (Page 407) ► Data RAM ► Demoduler RAM ► None of given options
Question No: 21 ( Marks: 1 ) - Please choose one The three fundamental gates are ___________
► AND, NAND, XOR ► OR, AND, NAND ► NOT, NOR, XOR ► NOT, OR, AND (Page 40)
Question No: 22 ( Marks: 1 ) - Please choose one
Which of the following statement is true regarding above block diagram?
► Triggering takes place on the negative-going edge of the CLK pulse ► Triggering takes place on the positive-going edge of the CLK pulse ► Triggering can take place anytime during the HIGH level of the CLK waveform ► Triggering can take place anytime during the LOW level of the CLK waveform
Question No: 23 ( Marks: 1 ) - Please choose one The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory ► The structure of memory ► The size of decoding unit ► The size of the address bus of the microprocessor (Page 430) rep
The basic building block for a logical circuit is _______
► A Flip-Flop ► A Logical Gate (Page 7) ► An Adder ► None of given options
Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
► Undefined ► One ► Zero (According to rule) ► No Output as input is invalid.
Question No: 5 ( Marks: 1 ) - Please choose one ________ is invalid number of cells in a single group formed by the adjacent cells in K-map ► 2 ► 8 ► 12 (According to rule “2^n” ) ► 16
Question No: 6 ( Marks: 1 ) - Please choose one The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder. ► AND (Page 182) ► OR ► NOT ► XOR
Question No: 7 ( Marks: 1 ) - Please choose one ___________ is one of the examples of synchronous inputs.
► J-K input (Page 235) rep ► EN input ► Preset input (PRE) ► Clear Input (CLR)
Question No: 8 ( Marks: 1 ) - Please choose one ___________ is one of the examples of asynchronous inputs.
► J-K input ► S-R input ► D input ► Clear Input (CLR) (Page 235)
The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369) rep ► Synchronous, asynchronous ► Preset input (PRE), Clear input (CLR) ► Clear input (CLR), Preset input (PRE)
Question No: 10 ( Marks: 1 ) - Please choose one __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
► Race condition ► Clock Skew (Page 226) rep ► Ripple Effect ► None of given options
Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________
► 0000 ► 1101 (not sure) ► 1011 ► 1111
Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 232) ► Current state and outputs ► Previous state and inputs ► Previous state and outputs
Question No: 13 ( Marks: 1 ) - Please choose one ________ is used to minimize the possible no. of states of a circuit.
► State assignment (Page 341) ► State reduction ► Next state table ► State diagram
Assume that a 4 - bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4 - bit pattern after the second clock pulse? (Right-most bit first.)
► 1100 ► 0011 ► 0000 Click here for detail rep ► 1111
Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by _______
► Depends on circuitry ► None of given options ► RAM ► Microprocessor (Page 397)
Question No: 21 ( Marks: 1 ) - Please choose one FIFO is an acronym for __________
► First In, First Out (Page 424) ► Fly in, Fly Out ► Fast in, Fast Out ► None of given options
Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for _________
► Look Up Table (Page 439) rep ► Local User Terminal ► Least Upper Time Period ► None of given options
Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation ________
► Vout / Vin = - Rf / Ri (Page 446) ► Vout / Rf = - Vin / Ri ► Rf / Vin = - Ri / Vout ► Rf / Vin = Ri / Vout
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output.
► Resolution ► Accuracy (Page 460) rep ► Quantization ► Missing Code
Question No: 25 ( Marks: 1 ) - Please choose one
Above is the circuit diagram of _______.
► Asynchronous up-counter (Page 270) ► Asynchronous down-counter ► Synchronous up-counter ► Synchronous down-counter
Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is ► n+2 (n plus 2) ► 2n (n multiplied by 2) (Page 354) ► 2 n^ (2 raise to power n) ► n^2 (n raise to power 2)
FINALTERM EXAMINATION
Spring 2010
Question No: 1 ( Marks: 1 ) - Please choose one "A + B = B + A" is __________
► Demorgan‟s Law ► Distributive Law ► Commutative Law (Page 72) ► Associative Law
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228) rep ► High-to-low transition of clock ► Enable input (EN) is set ► Preset input (PRE) is set
Question No: 8 ( Marks: 1 ) - Please choose one A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
► 10 mW ► 25 mW (Page 242) ► 64 mW ► 1024
Question No: 9 ( Marks: 1 ) - Please choose one ____________ counters as the name indicates are not triggered simultaneously.
► Asynchronous (Page 269) ► Synchronous ► Positive-Edge triggered ► Negative-Edge triggered
Question No: 10 ( Marks: 1 ) - Please choose one 74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285) rep ► ENI, ENC ► ENP, ENC ► ENT, ENI
Question No: 11 ( Marks: 1 ) - Please choose one The divide-by- 60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod- 10 (Page 299) ► Mod-50, Mod- 10 ► Mod-10, Mod- 50 ► Mod-50, Mod- 6
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 332) ► Current state and outputs ► Previous state and inputs ► Previous state and outputs
Question No: 13 ( Marks: 1 ) - Please choose one A synchronous decade counter will have _______ flip-flops
► 3 ► 4 (Page 281) ► 7 ► 10
Question No: 14 ( Marks: 1 ) - Please choose one ________ is used to minimize the possible no. of states of a circuit.
► State assignment (Page 341) rep ► State reduction ► Next state table ► State diagram
Question No: 15 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts _________
► Serial data to parallel ► Parallel data to serial (Page 356) rep ► Serial data to serial ► Parallel data to parallel
Question No: 16 ( Marks: 1 ) - Please choose one The alternate solution for a demultiplexer-register combination circuit is _________
► Parallel in / Serial out shift register ► Serial in / Parallel out shift register (Page 356) ► Parallel in / Parallel out shift register ► Serial in / Serial Out shift register
Question No: 17 ( Marks: 1 ) - Please choose one A GAL is essentially a ________. ► Non-reprogrammable PAL ► PAL that is programmed only by the manufacturer ► Very large PAL ► Reprogrammable PAL (Page 183) rep
