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Analog to Digital Convertion
Involves converting the analogue signals into binary words.The basic elements of ADC is shown below: A clock supplies regular signal pulses to the ADC andevery time it receives a pulse it samples the analoguesignal^ A sample and hold unitis used to hold eachsampled value until thenext pulse occurs.
The
S/H unit is necessarybecause the ADconverter requires afinite amount of timetermed the conversiontime
, to convert the
analogue signal into adigital one
Quantization time
≅^4
μS
AD Convertion
Consider an ADC of 3 bit word then: The possible output levels is 2
output levels, there ıs a range ofoutput for which the input does notchange
The 8 possible output levels aretermed
quantization level
The difference in analoguevoltage between two adjacentlevels is termed
quantization
interval
(=1 volt in Fig.; step like
nature) The digital output is not always equal tothe analogue input value and thus therewill be an error termed
quantization
error
. When the input is centered over the interval, the quantization error iszero. The maximum error being equal to½ of interval or
±½ bit
Sampling theorem (1)
-^
Nyquist’s Criteria or Shannon’s theorem^ –
An Analog signal with a highest frequency of f
a
MUST
be sampled at a rate f
> 2fs
to avoid loss ofa
information.
-^
If f
< 2fs
then a phenomena called aliasing will occura
in the analog signal bandwidth Aliasing: When the sampling rate is less than twice thehighest frequency, the reconstruction can represent someother analogue signal and we obtain a false image.An anti-aliasing filter is used precede the ADC, the filterhaving a band width such that it passes only lowfrequencies for which sampling rate will not give aliasingerrors
Sampling theorem (2)
Aliasingexamples
Successive approximations ADC is the most commonly used method. A voltage isgenerated by a clock emitting a regular sequence of pulses which are counted inbinary manner, and the resulting word converted into an analogue voltage byDAC. This voltage rises in step and is compared with the analogue input voltagefrom the sensor. When the generated voltage passes the input sensor voltage, thepulses from the clock are stopped. The output from the counter at that time is thedigital representation of the analogue voltage. Faster successive method is alsopossible
Analog to Digital Converter
Successiveapproximations ADC
Successive approximations
ZN
ADC outlines
Analog to Digital Converter
Zero voltageterminal
Ramp ADC:
Involve an analogue voltage which is increased at a constant
rate, and applied to a comparator, where it is compared with analogue sensorvoltage. When the ramp voltage starts, a gate is opened which starts a binarycounter counting the regular pulses from the clock. When the two voltages areequal, the clock stop counting and the counter value indicate the equivalentdigital value of the sampled one
Analog to Digital Converter
Ramp ADC
Thus when the analogue voltage is applied to ADC, all those comparator for whichthe analogue voltage is greater than the reference voltage will give a high outputand those below the reference will give a low output. The resulting output are fedin parallel to a logic gate system which translate them into a digital word
AD Flash Converter
Flash ADC is very fasttype of ADC .For n bitconverter, 2n-1 separatevoltage comparators areused in parallel, witheach having theanalogue input voltageas one input. Thereference voltage isapplied to a ladder ofresistors, so the voltageapplied as other input toeach comparator is onebit large in size than thevoltage applied to theprevious comparator inthe ladder
DAC Binary Weighted Principles
f
out
n
n
n
n
REF
R I V b b b b
V R
I^
0
(^10)
(^21)
1 2
0 1
0
2
2 ... 2
2
−
⇒
^
− =^
−
−
−
−
I= sum of currents^0 leaving the junctionR= resistance toLSBn= number of inputbitsb= bit status (1=ONor 0=OFF)
DAC Example
Find output voltage and current for a binaryweighted resistor DAC of 4 bits whereR = 10 k Ohms, R
= 5 kf
O
hms and V
ref
= 10
Volts. Applied binary word is 1001.
V
A
k
I V
V k
Io
(^625). 5 )
(^001125). 0 )( (^5) (
I R-
V
A
0.001125-
(^12)
(^02)
(^02) (^12)
(^1010)
0
0 f
0 0
3
2 1 0
=
− Ω − = = =
^
Solution:
R
R
ladder DAC
½ I
¼ I
1 /^8
I^
1 /^16
I
More commonly used, only two values of resistors are required.The output is generated by switching the weighted referencevoltage either to the
–ive
input terminal of the opamp or to the
earth terminal depending on the value of the digital input binaryvalue (0 or 1)
DAC structure ZN558D
PC-LPM-16 DAQ board
Typical DAQ Board
