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An overview of xilinx fpga memory types, focusing on distributed ram and block ram. It explains the differences between these two types, their configurations, and their use cases. The document also includes vhdl code examples for distributed ram with asynchronous read and distributed dual-port ram with asynchronous read.
Typology: Study notes
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Outline
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The Design Warriorās Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright Ā© 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx Multipurpose LUT
RAM16X1S
O
D WE WCLK A A A A RAM32X1S
O
D WE WCLK A A A A A RAM16X2S
O
D WE WCLK A A A A
D O
=
=
LUT
LUT or
LUT
RAM16X1D
SPO
D WE WCLK A A A A DPRA0 DPO DPRA DPRA DPRA
or
Distributed RAM
9
Spartan- Dual-Port Block RAM
13
0
16,
1
4,
4 0
8,
2 0
2047
8+ 0
1023
16+ 0
Block RAM Port Aspect Ratios
15
Single-Port Block RAM
Dual-Port Block RAM
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21
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Distributed RAM with asynchronous read
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;
entity raminfr is generic ( bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(bits-1 downto 0); do : out std_logic_vector(bits-1 downto 0)); end raminfr;
Distributed RAM with asynchronous read
architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits- downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; end if; end process; do <= RAM(conv_integer(unsigned(a))); end behavioral;
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Report from Synthesis
Resource Usage Report for raminfr
Mapping to part: xc3s50pq208-
Cell usage:
GND 1 use
RAM16X4S 8 uses
I/O ports: 69
I/O primitives: 68 IBUF 36 uses
OBUF 32 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 0 (0%)
RAM/ROM usage summary
Single Port Rams (RAM16X4S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 32 (2%)
Report from Implementation
Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of occupied Slices: 16 out of 768 2% Number of Slices containing only related logic: 16 out of 16 100% Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 32 out of 1,536 2% Number used as 16x1 RAMs: 32 Number of bonded IOBs: 69 out of 124 55% Number of GCLKs: 1 out of 8 12%
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architecture behavioral of raminfr is type ram_type is array (2**addr_bits-1 downto 0) of std_logic_vector (bits- downto 0); signal RAM : ram_type; begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(unsigned(a))) <= di; end if; do <= RAM(conv_integer(unsigned(a))); end if; end process;
end behavioral;
Report from Synthesis
Resource Usage Report for raminfr Mapping to part: xc3s50pq208- Cell usage: FD 32 uses GND 1 use RAM16X4S 8 uses I/O ports: 69 I/O primitives: 68 IBUF 36 uses OBUF 32 uses BUFGP 1 use
I/O Register bits: 0 Register bits not including I/Os: 32 (2%)
RAM/ROM usage summary Single Port Rams (RAM16X4S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary: Total LUTs: 32 (2%)
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Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 32 out of 1,536 2%
Logic Distribution:
Number of occupied Slices: 16 out of 768 2% Number of Slices containing only related logic: 16 out of 16 100% Number of Slices containing unrelated logic: 0 out of 16 0% *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 32 out of 1,536 2%
Number used as 16x1 RAMs: 32 Number of bonded IOBs: 69 out of 124 55% Number of GCLKs: 1 out of 8 12%
Total equivalent gate count for design: 4,
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Report from Synthesis
Resource Usage Report for raminfr
Mapping to part: xc3s50pq208-
Cell usage:
GND 1 use
RAMB16_S36 1 use
VCC 1 use
I/O ports: 69 I/O primitives: 68
IBUF 36 uses
OBUF 32 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 0 (0%)
RAM/ROM usage summary
Block Rams : 1 of 4 (25%)
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 0 (0%)
Report from Implementation
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Logic Distribution:
Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 69 out of 124 55% Number of Block RAMs: 1 out of 4 25% Number of GCLKs: 1 out of 8 12%
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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
entity raminfr is generic ( bits : integer := 32; -- number of bits per RAM word addr_bits : integer := 3); -- 2^addr_bits = number of words in RAM
port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(addr_bits-1 downto 0); dpra : in std_logic_vector(addr_bits-1 downto 0); di : in std_logic_vector(bits-1 downto 0); spo : out std_logic_vector(bits-1 downto 0); dpo : out std_logic_vector(bits-1 downto 0)); end raminfr;
