Direct Map Cache and Set Associative Cache (Revision), Summaries of Computer Science

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Direct Map Cache and Set

Associative Cache (Revision)

Lecture 14 CDA 3103 07 - 07 - 2014

Example 1

 A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.

Example 2

 A two-way set-associative cache has lines of 16 bytes and a total size of 8 kbytes. The 64-Mbyte main memory is byte addressable. Show the format of main memory addresses.

Solution

 There are a total of 8 kbytes/16 bytes = 512 lines in the cache. Thus the cache consists of 256 sets of 2 lines each. Therefore 8 bits are needed to identify the set number. For the 64-Mbyte main memory, a 26-bit address is needed. Main memory consists of 64-Mbyte/16 bytes = 2 22 blocks. Therefore, the set plus tag lengths must be 22 bits, so the tag length is 14 bits and the word field length is 4 bits.

Solution 3a

Example 3 (continued)

 b. Into what line would bytes with each of the following addresses be stored?  0001 0001 0001 1011  1100 0011 0011 0100  1101 0000 0001 1101  1010 1010 1010 1010

Example 3 (continued)

 c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it?  d. How many total bytes of memory can be stored in the cache?  e. Why is the tag also stored in the cache?

Solution 3 (continued)

 c. Bytes with addresses 0001 1010 0001 1000 through 0001 1010 0001 1111 are stored in the cache.  d. 256 bytes.  e. Because two items with two different memory addresses can be stored in the same place in the cache. The tag is used to distinguish between them.

Solution 5

 a. Address format: Tag = 20 bits; Line = 6 bits; Word = 6 bits. Number of addressable units = 2 32 bytes; number of blocks in main memory = 2 26 ; Number of lines in cache = 2 6 = 64; size of tag = 20 bits.  b. Address format: Tag = 26 bits; Word = 6 bits. Number of addressable units = 2^32 bytes; number of blocks in main memory = 226 ; Number of lines in cache = undetermined; size of tag = 26 bits.  c. Address format: Tag = 9 bits; Set = 17 bits; Word = 6 bits. Number of addressable units = 2 32 bytes; Number of blocks in main memory = 2 26 ; Number of lines in set = k = 4; Number of sets in cache = 2 17 ; Number of lines in cache = 2 19 ; Size of tag = 9 bits.

Question 6

 6. Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.  a. For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag, cache line address, and word offsets for a direct- mapped cache.  b. Give any two main memory addresses with different tags that map to the same cache slot for a direct-mapped cache.  c. For the main memory addresses of F0010 and CABBE, give the corresponding tag and offset values for a fully-associative cache.  d. For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache set, and offset values for a two-way set- associative cache.

Solution 6a (continued)

 F0010 = 1111 0000 0000 0001 0000 Word offset = 0000 = 0 Line = 0000 0000 0001 = 001 Tag = 1111 = F  01234 = 0000 0001 0010 0011 0100 Word offset = 0100 = 4 Line = 0001 0010 0011 = 123 Tag = 0000 = 0  CABBE = 1100 1010 1011 1011 1110 Word offset = 1110 = E Line = 1010 1011 1011 = ABB Tag = 1100 = C

Solution 6b

 b. We need to pick any address where the line is the same, but the tag (and optionally, the word offset) is different. Here are two examples where the line is 1111 1111 1111  Address 1: Word offset = 1111 Line = 1111 1111 1111 Tag = 0000 Address = 0FFFF  Address 2: Word offset = 0001 Line = 1111 1111 1111 Tag = 0011 Address = 3FFF

Solution 6d

 d. As computed in part a, we have 4096 cache lines. If we implement a two – way set associative cache, then it means that we put two cache lines into one set. Our cache now holds 4096/2 = 2048 sets, where each set has two lines. To address these 2048 sets we need 11 bits (2^11 = 2048). Once we address a set, we will simultaneously search both cache lines to see if one has a tag that matches the target. Our 20 - bit address is now broken up as follows:  Bits 0-3 indicate the word offset  Bits 4-14 indicate the cache set  Bits 15-20 indicate the tag  F0010 = 1111 0000 0000 0001 0000 Word offset = 0000 = 0 Cache Set = 000 0000 0001 = 001 Tag = 11110 = 1 1110 = 1E  CABBE = 1100 1010 1011 1011 1110 Word offset = 1110 = E Cache Set = 010 1011 1011 = 2BB Tag = 11001 = 1 1001 = 19