Computer Architecture Lecture 6: Divide, Floating Point, Pentium Bug, Slides of Computer Science

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CS 152: Computer Architecture

and Engineering

Lecture 6

Divide, Floating Point, Pentium Bug

Divide: Paper & Pencil

1001 Quotient

Divisor 1000 1001010 Dividend

• 10 101 1010

10 Remainder (or Modulo result)

See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor

Dividend = Quotient x Divisor + Remainder => | Dividend | = | Quotient | + | Divisor |

3 versions of divide, successive refinement

2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0.

Divide Algorithm Version 1

Takes n+1 steps for n-bit Quotient & Rem.

Remainder Quotient Divisor 0000 0111 0000 0010 0000

Test Remainder

Remainder ≥ 0 Remainder < 0

1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.

2a. Shift the Quotient register to the left setting the new rightmost bit to 1.

3. Shift the Divisor register right1 bit.

Done

Yes: n+1 repetitions (n = 4 here)

Start: Place Dividend in Remainder

n+ repetition?

No: < n+1 repetitions

Divide Algorithm I Example (7 / 2)

Remainder Quotient Divisor

Divide Algorithm I Example: Wasted Space

Remainder Quotient Divisor

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  • Quotient = Answer:
  • Remainder =
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Divide: Paper & Pencil

01010 Quotient

Divisor 0001 00001010 Dividend 00001

• 0000 0001
  • 0 00 Remainder (or Modulo result)
• Notice that there is no way to get a 1 in leading digit! (this

would be an overflow, since quotient would have n+1 bits)

Divide Algorithm Version 2

Remainder Quotient Divisor

3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0.

Test Remainder

Remainder ≥ (^0) Remainder < 0

2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.

3a. Shift the Quotient register to the left setting the new rightmost bit to 1.

1. Shift the Remainder register left 1 bit.

Done

Yes: n repetitions (n = 4 here)

nth repetition?

No: < n repetitions

Start: Place Dividend in Remainder

Observations on Divide Version 2

 Eliminate Quotient register by combining with

Remainder as shifted left

• Start by shifting the Remainder left as before.
• Thereafter loop contains only two steps because the shifting

of the Remainder register shifts both the remainder in the

left half and the quotient in the right half

• The consequence of combining the two registers together and

the new order of the operations in the loop is that the

remainder will shifted left one time too many.

• Thus the final correction step must shift back only the

remainder in the left half of the register

Divide Algorithm Version 3

Remainder Divisor

3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0.

Test Remainder

Remainder ≥ 0 Remainder < 0

2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.

3a. Shift the Remainder register to the left setting the new rightmost bit to 1.

1. Shift the Remainder register left 1 bit.

Done. Shift left half of Remainder right 1 bit.

Yes: n repetitions (n = 4 here)

nth repetition?

No: < n repetitions

Start: Place Dividend in Remainder

Observations on Divide Version 3

 Same Hardware as Multiply: just need ALU to add or

subtract, and 64-bit register to shift left or shift

right

 Hi and Lo registers in MIPS combine to act as 64-bit

register for multiply and divide

 Signed Divides: Simplest is to remember signs, make

positive, and complement quotient and remainder if

necessary

• Note: Dividend and Remainder must have same sign
• Note: Quotient negated if Divisor sign & Dividend sign

disagree

e.g., –7 ÷ 2 = –3, remainder = –

• What about? –7 ÷ 2 = –4, remainder = +

Recall Scientific Notation

6.02 x 10 1.673 x 10

exponent

Mantissa^ radix (base)

decimal point

Sign, magnitude

Sign, magnitude

IEEE F.P. ± 1.M x 2

e - 127

 Issues:

• Arithmetic (+, -, *, / )
• Representation, Normal form
• Range and Precision
• Rounding
• Exceptions (e.g., divide by zero, overflow, underflow)
• Errors
• Properties ( negation, inversion, if A ≠ B then A - B ≠ 0 )

Review from Prerequisties: Floating-Point Arithmetic

Representation of floating point numbers in IEEE 754 standard:

single precision

sign

exponent:

excess 127 binary integer

mantissa:

sign + magnitude, normalized binary significand w/ hidden integer bit: 1.M

actual exponent is e = E - 127

S E M

N = (-1) 2 (1.M)

S E-

0 < E < 255

Magnitude of numbers that can be represented is in the range:

(1.0) (^) to 2

which is approximately:

1.8 x 10

to 3.40 x 10

Extra Bits for Rounding

"Floating Point numbers are like piles of sand; every time you move

one you lose a little sand, but you pick up a little dirt."

How many extra bits?

IEEE: As if computed the result exactly and rounded.

Addition:

1.xxxxx 1.xxxxx 1.xxxxx

• 1.xxxxx 0.001xxxxx 0.01xxxxx

1x.xxxxy 1.xxxxxyyy 1x.xxxxyyy

post-normalization pre-normalization pre and post

 Guard Digits: digits to the right of the first p digits of

significand to guard against loss of digits – can later be shifted

left into first P places during normalization.

 Addition: carry-out shifted in

 Subtraction: borrow digit and guard

 Multiplication: carry and guard, Division requires guard

Rounding Digits

Normalized result, but some non-zero digits to the right of the significand --> the number should be rounded

E.g., B = 10, p = 3: 0 2 1.

0 0 7.

0 2 1.

2-bias

2-bias

2-bias

one round digit must be carried to the right of the guard digit so that after a normalizing left shift, the result can be rounded, according to the value of the round digit

IEEE Standard:

four rounding modes: round to nearest even (default) round towards plus infinity round towards minus infinity round towards 0 round to nearest: round digit < B/2 then truncate

B/2 then round up (add 1 to ULP: unit in last place) = B/2 then round to nearest even digit

it can be shown that this strategy minimizes the mean error

introduced by rounding