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Main points of this exam paper are: Double-Poly Capacitor, Construction, Parasitic Capacitors, Switched Capacitor Integrator, Parasitic Capacitors, Various Stages, Architecture
Typology: Exams
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There are two sections (A and B) Examiners: Prof. G. Hurley Dr. S. Foley Answer any five questions Dr. J. Barrett Mr. P. Collins Please use separate answer books for each section.
Each question carries equal marks (20)
Maximum available mark is 100.
(a) Outline the construction of a double-poly capacitor. Show where parasitic capacitors arise in it’s construction. [ 5 marks ]
(b) Draw the circuit diagram of a switched capacitor integrator and derive the sampled data transfer function. Ignore any parasitic capacitors in the circuit. [ 5 marks ]
(c) Draw the circuit diagram of a switched capacitor integrator which is insensitive to parasitic capacitances found in a poly-poly capacitor. Derive the sampled data transfer function. Explain clearly how the effect of any parasitic capacitors are removed. [ 10 marks ]
Q2. (a) Give a block diagram of the architecture of a Delta-Sigma ADC. Explain the function of the various stages of the ADC. [ 4 marks ]
(b) Explain how a 1 st^ order delta-sigma modulator can be used to shape the quantization noise of a quantizer. Make reference to the noise transfer function and the signal transfer function in your explanation. [ 4 marks ]
(c) The magnitude of the Noise Transfer Function of a 1 st^ order delta-sigma
modulator is (^)
f S
f NTF Sin
3
f (^) S is the sampling frequency of the ADC. f (^) O is the frequency range of interest on the input. OSR = f (^) S/2f (^) O. ∆ is the LSB size.
Spectral density of the quantization noise is S
E f
[ 6 marks ]
(d) Using the equation for P (^) E from part (c) , show that the maximum SNR of a 1 st order delta-sigma N-bit ADC = 6.02N + 1.76 - 5.17 + 30*log 10 (OSR) for a sine wave input signal. [ 6 marks ]
Q5. Impedance matching
(a) Why is impedance matching necessary in RF circuits? (2 marks)
(b) A 50Ω microstrip transmission line is to be used to feed an antenna which represents a load impedance of (25-j40) Ω. Use the Smith Chart provided to find the distance from the load and length of a shunt open transmission line stub that will match the microstrip line to the antenna at 2.5GHz. Assume a phase velocity of 2.7x10 8 m/s. (7 marks)
(c) Use the Smith Chart to design a two-element lumped LC matching network, blocking DC, to match the 50Ω microstrip line to the antenna of Part (b) above at 2.5GHz. (7 marks)
(d) At 2.5GHz, is the stub matching network or the lumped element matching network preferable? Why? (4 marks)
Q6. S-parameters and small signal amplifiers
(a) Outline the advantages of using s-parameters for small signal amplifier design. (2 marks)
(b) List the three main types of circle that can be generated on the Smith Chart using transistor s-parameters and outline how they are used in small signal amplifier design (6 marks)
(c) When is “simultaneous conjugate matching” used in small signal amplifier design? (2 marks)
(d) A transistor has the following s-parameters at 800MHz
(i) Calculate the maximum available gain, assuming unilaterality (2 marks) (ii) Check if the assumption of unilaterality is valid (2 marks) (iii) Match this transistor to a 50Ω source and a load of (40+j60)Ω using two- element lumped L-C matching networks, blocking DC, at 800MHz to obtain maximum available gain assuming unilaterality (6 marks)
The following formulae may be found useful:
21 22
11 12 s s
s s S
2 22
2 2 21 11
( ) 1
s
s s
G (^) TUMax −
11 12 21 22 2 2 1 1
where 1
s s
s s s s U G U
T − −
Q7. RF Power amplifiers
(a) Draw a simple power supply network for the collector of a power transistor that prevents RF signals entering the DC supply. (2 marks)
(b) Outline the causes of intermodulation distortion and explain why a two-tone test is used to measure it. (4 marks)
(c) Using Figure Q7.1 below from the data sheet of an RF power transistor, identify the transistor’s intermodulation distortion at 960MHz. (2 marks)
Figure Q7. (d) In relation to Figure Q7.2 below
i. What is “ACPR”? (2 marks) ii. Why is ACPR important in RF communications? (2 marks)
Figure Q7.
Question 7 continued on next page
Q8. Oscillators and mixers
(a) The active device in a negative resistance oscillator has a negative resistance varying linearly with its current (I 0 ) as shown in Figure Q8. Assuming that device reactance is negligible, show that, for maximum oscillator power output, the diode should be presented with a load resistance of one third the start-up resistance of the active device i.e.: (8 marks)
Figure Q
(b) Given R (^) L = RD(0)/3, find the impedance of the load tuning network that will give maximum output power from a one-port negative resistance oscillator using a diode with Γin = 1.6∠-65° in a 50Ω system (4 marks)
(c) What is an “image reject mixer” and why is it needed? (4 marks)
(d) Briefly give definitions for the following terms used in describing mixers: “high side injection”, “conversion loss”, “compression”, and “noise factor” (4 marks)
RL =− RD (max) = Rm = RD
RD(Io )
-R (^) m
Io(Max)
R (^) D(Max)
R (^) L (^) R (^) D(Io )
APPENDIX A: VHDL Language Reference
_An underscore in front of a word means that it is replaced by the appropriate VHDL construct in practice. ( e.g. _signal_name is replaced by a valid VHDL signal name , statement is replace by a valid VHDL statement ).
----- Library declaration.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL;
----- Architecture declaration.
_ARCHITECTURE a OF _entity_name IS
_----- SIGNAL declaration SIGNAL __signal_name : STD_LOGIC; SIGNAL _signal_name : STD_LOGIC;
----- COMPONENT declaration ( if needed ).
BEGIN
END a;
----- Case statement.
_CASE __expression IS WHEN __constant_value => __statement; __statement; WHEN __constant_value => __statement; __statement; WHEN OTHERS => __statement; _statement; END CASE;
----- Component declaration.
_COMPONENT __component_name PORT( __input_name, __input_name : IN STD_LOGIC; __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, _output_name : OUT STD_LOGIC); END COMPONENT;
----- Component instantiation.
___instance_name: __component_name PORT MAP (__component_port => __connect_port, __component_port => _connect_port);
___label: WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN _constant_value;
------ Signal declaration.
_SIGNAL __signal_name : _type_name;
----- Signal assignment.
___signal_name <= _expression;
----- State machine with asynchronous reset.
_ENTITY __machine_name IS PORT( Clk : IN STD_LOGIC; Reset : IN STD_LOGIC; __input_name, __input_name : IN STD_LOGIC; __output_name, __output_name: OUT STD_LOGIC); END _machine_name;
_ARCHITECTURE a OF __machine_name IS TYPE STATE_TYPE IS (__state_name, __state_name, __state_name); SIGNAL state: STATE_TYPE; BEGIN PROCESS (clk) BEGIN IF reset = '1' THEN state <= _state_name; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN __state_name => IF __condition THEN state <= __state_name; END IF; WHEN __state_name => IF __condition THEN state <= __state_name; END IF; WHEN __state_name => IF __condition THEN state <= _state_name; END IF; END CASE; END IF; END PROCESS;
_WITH state SELECT __output_name <=__output_value WHEN __state_name, __output_value WHEN __state_name, __output_value WHEN _state_name; END a;
