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Main points of this past exam are: Down Network, Pull-Down Network, Simplified Expression, Minimum Number, Literals, Boolean Identities, Minimum Number, Binary Function, Single Literals Only, Simplified Product-Of-Sum
Typology: Exams
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Prob 1 (20pts)
Prob 2 (25pts)
Prob 3 (25pts) Prob 4 (30pts)
TOTAL (100pts)
a) (13pts) give a simplified expression of F. The expression should contain the minimum number of literals.
F bad d c b bad d c b b a d dc b
bad d c b
cdb ba b d d c b
bd bc cd b ba b d d c b
F b c d c b ba b d d cb
b) (7pts) draw the corresponding pull-up network using the result from part a). Assume that complemented inputs are available.
b
a (^) d
b
d
c
b
b c
d c
b
b
a b
d
d c
F( a,b,c,d)= (^) ∑ m( 1 , 3 , 4 , 8 , 9 , 11 , 13 , 15 )+ ∑DC( 5 , 14 )
a) (9pts) draw the corresponding K-map. Replace don’t cares with 0s and 1s so that your final POS expressions contain the minimum number of literals.
Bold entries denote the don’t care replacement.
b) (9pts) give the expressions for prime implicants, essential prime implicants, and non-essential prime implicants.
Prime implicants: cd = c+d,abd=a+b+d,abc=a+b+c,abd=a+b+d Essential prime implicants: c + d,a+b+d,a+b+c,a+b+d Non-essential prime implicants: none
c) (7pts) give all possible simplified POS expressions of F.
F =( c+d)(a+b+d)(a+b+c)(a+b+d)
a
d
c
b
F (a,b,c,d,e)= b(c+e)+a+a+c d
a) (10pts) implement a gate-level network of F using NAND gates and inverters only. Use the mixed logic method, and do not simplify F. Assume that complemented inputs are not available.
b) (15pts) implement a CMOS switch-level network of F so that it contains a single pair of pull-down and pull-up networks. Assume that complemented inputs are available.
F ab ace a b a c e
b ce a ab ace
b ce a ac ad
b ce a ac d
b c e a a cd
b c e a a cd
F bc e a a cd
b c e a a c d