ECE Laboratory Electronics Engineer, Lab Reports of Electronics engineering

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ELECTRONICS

CIRCUITS

ANALYSIS and

DESIGN ACTIVITY

JFET

FUNDAMENTALS

RACELIS, JOHN FERNAND N.

BSECEIII

RUBRICS FOR ECE02 LABORATORY

Attribute 1 - Not Acceptable 2 - Below Expectations 3 - Meets Expectations 4 - Exceeds Expectations Score Laboratory Skills Manipulative Skills Members do not demonstrate needed skills Members occasionally demonstrate needed skills Members occasionally demonstrate needed skills Members demonstrate additional skills Safety Precautions Damage to circuits or equipment due to improper usage Some risk to circuits or equipment due to improper usage Equipment usage safe for both circuits and equipment Safety precautions above requirements used Experimental Set-up Apparatus set up in a non- functional manner Apparatus setup will cause data errors Apparatus properly setup Apparatus enhance for better precision Process Skills Errors in documentation of apparatus Error in documentation of procedures Documentation complete and correct Report warns of difficulties and gives alternatives Reports logically coherent and sequential Conditions for data and/or graphs not stated. Unclear report All data present, but not in sequence. Must search for items. Data presented clearly following each procedure. Data presented clearly along with excellent narrative Work Habits Time management/Conduct of Experiment Required data not taken or not reported Data points poorly chosen or missing All required data taken and reported Measurements beyond requirements made and reported Ability to draw proper conclusions from lab Conclusions not drawn Incorrect conclusions drawn Correct conclusions drawn Correct conclusions correlated to other material Cooperative and teamwork Members do not know their task and have no defined responsibilities. Group conflicts have to be settled by the teacher Members have defined responsibilities sometimes. Group conflicts are cooperatively managed most of the time Members have defined responsibilities most of the time. Group conflicts are cooperatively managed most of the time Members are on task and have responsibilities at all-time. Group conflicts are cooperatively managed at all times Neatness and orderliness Messy workplace/paper during and after experiment Clean and orderly workplace/papers with occasional mess during and after experiment Clean and orderly workplace/papers with some mess during and after experiment Clean and orderly workplace/papers at all times during and after experiments Ability to do independent work Members require supervision by the teacher Members require occasional supervision by the teacher Members do not supervised by the teacher Members demonstrate other ability Spelling and grammar Many errors Several errors No more than two errors No errors Computer use For data analysis Not done Done incorrectly Done correctly but incomplete^ Done correctly and completely

Figure4.1 Structure and Symbol of FET REQUIREMENTS: Power supply: two independent low-voltage variable supplies. DMM FET transistor 2N Multisim Software PROCEDURE: Fig. 4.2. Zero Gate Bias JFET Test Circuit Fig. 4.3. Gate Bias JFET Test Circuit DRAINCHARACTERISTICS Effect of Drain Voltage on Drain Current at Zero Gate Bias

1. Connect the Zero gate bias JFET Test circuit, as shown in circuit 4-2.
2. Adjust^ the^ drain^ supply^ VDD to^ each^ value^ listed^ in^ Table^ 4-1.^ Measure^ the corresponding voltage drop across drain resistor R 3 , then compute for the equivalent drain current ID
3. Plot the drain characteristics curve in Graph 4 - 1 using the data from Table 4 - 1. Mark the value of pinch-off voltage Vp in the graph. Effect of Drain Voltage on Drain Current with Gate Bias
4. Connect the Gate Bias JFET circuit, as shown in circuit 4.
5. Set^ the^ gate^ supply^ VGG to^ -0.5^ V.^ Change^ the^ drain^ supply^ VDD to^ each^ value listed in Table 4-2. Get the resultant voltage drop across drain resistor R 3 , then calculate the drain current ID.
6. Set^ the^ gate^ supply^ VGGTO^ -3^ V.^ Change^ the^ drain^ supply^ VDD to^ each^ value^ listed^ in Table 4-2. Get the resultant voltage drop across drain resistor R 3 , then calculate drain current ID.
7. Plot^ the^ drain^ characteristics^ curve^ for^ VGG at^ 0.5^ V^ and^ VGG at^ -3^ V^ in^ Graph^ 4.2. Use the data (^) from Table 4.2. Label property the graph of different gate bias. Identify the value of respective pinch-off voltage in the graph. JFET TRANSFER CHARACTERISTICS Effect of the Gate Bias on Drain Current
8. Use the Gate Bias JFET Test Circuit shown in Fig. 4.2.

DATA AND TABLE PRESENTATION OF MULTISIM

Table 4.1 Drain Supply vs. Drain Current with Zero Gate Bias Gate Supply VGG=0 VDC Drain Supply VDD(VDC) Drain Current ID(mA) Voltage Drop 0 V 0 A 0 V 1 V 1.795 mA 0.159 V 2 V 2.423 mA 0.238 V 3 V 2.428 mA 0.243 V 4 V 2.433 mA 0.243 V 5 V 2.438 mA 0.244 V 6 V 2.442 mA 0.244 V 7 V 2.448 mA 0.245 V 8 V 2.452 mA 0.245 V 9 V 2.457 mA 0.246 V 10 V 2.462 mA 0.246 V 11 V 2.466 mA 0.247 V 12 V 2.471 mA 0.247 V Table 4.2 Drain Supply vs. Drain Current with Gate Bias Gate Supply VGG =- 0. 5 VDC Gate Supply VGG =-3 VDC Drain Supply VDD (VDC) Drain Current

ID ( mA )

Voltage Drop Drain Supply VDD (VDC) Drain Current

ID ( mA )

Voltage Drop 0 V 1.029 pA 81.192 pV 0 V 3.505 pA 350.460 pA 1 V 1.277 mA^ 0.119 V^ 1 V 0 A^ 706.350 pA 2 V 1.450 mA^ 0.145 V^ 2 V 0 A^ 1.061 nV 3 V 1.453 mA 0.145 V 3 V 0 A 1.416 nV 4 V 1.456 mA^ 0.146 V^ 4 V 0 A^ 1.770 nV 5 V 1.459 mA^ 0.146 V^ 5 V 0 A^ 2.125 nV 6 V 1.461 mA^ 0.146 V^ 6 V 0 A^ 2.479 nV 7 V 1.465 mA^ 0.146 V^ 7 V 0 A^ 2.833 nV 8 V 1.467 mA^ 0.146 V^ 8 V 0 A^ 3.186 nV 9 V 1.469 mA^ 0.147 V^ 9 V 0 A^ 3.540 nV 10 V 1.474 mA^ 0.147 V^ 10 V 0 A^ 3.893 nV 11 V 1.476 mA^ 0.148 V^ 11 V 0 A^ 4.247 nV 12 V 1.478 mA^ 0.148 V^ 12 V 0 A^ 4.599 nV

Gate Supply VDD = 4 VDC Gate Supply VDD =8 VDC Gate Supply VGG (VDC) Drain Current

ID ( mA )

Voltage Drop Gate Supply VGG (VDC) Drain Current

ID ( mA )

Voltage Drop 0 V 2.433 mA^ 0.243 V^ 0 V 2.452 mA^ 0.245 V 1 V 4.920 mA^ 0.492 V^ 1 V 4.953 mA^ 0.495 V 2 V 5.640 mA^ 0.539 V^ 2 V 5.696 mA^ 0.569 V 3 V 4.917 mA^ 0.413 V^ 3 V 5.775 mA^ 0.576 V 4 V 2.625 mA^ 0.198 V^ 4 V 5.809 mA^ 0.580 V 5 V -0.228 A -0.332 V 5 V 5.830 mA 0.582 V 6 V -1.185 A^ -1.290 V^ 6 V 5.841 mA^ 0.557 V 7 V -2.169 A^ 2.265 V^ 7 V 5.044 mA^ 0.423 V 8 V -3.160 A -3.246 V 8 V 2.717 mA 0.205 V 9 V -4.153 A^ -4.229 V^ 9 V -0.228 A^ -0.335 V 10 V -5.147 A^ -5.699 V^ 10 V -1.185 A^ -1.289 V 11 V -6.143 A^ -6.200 V^ 11 V -2.169 A^ -2.265 V 12 V -7.139 A^ -7.691 V^ 12 V -3.160 A^ -3.246 V PINCH OFF VOLTAGE Gate Supply: 4 VDc Gate Supply: 8 VDc Result (Vp) Voltage Drop Voltage Drop 0.243 V 0.245 V 0.020 V 0.492 V 0.495 V 0.030 V 0.539 V 0.569 V 0.030 V 0.413 V 0.576 V 0.163 V 0.198 V 0.580 V 0.382 V -0.332 V 0.582 V 0.250 V -1.290 V 0.557 V 0.733 V 2.265 V 0.423 V 1.842 V -3.246 V 0.205 V 3.041 V -4.229 V -0.335 V 3.894 V -5.699 V -1.289 V 4.410 V -6.200 V -2.265 V 3.935 V -7.691 V -3.246 V 4.445 V GRAPH

affected and will keep on increasing but if there is a voltage flowing in the gate, the current reading will be affected. Sometimes, it can lead to a negative reading or just no current at all.  What I have seen in the second simulation is the changing of the Values of Vdd (Drain Supply) and keeping the Vgg in constant voltage of -0.5 V and - V. In this simulation, I have noticed that as the Vdd values increases, the probability of dropped currents increases.  The polarity in the gate bias also has an effect to the drain current wherein it often displays a zero current or negative current just like in Vgg = -3V. On the other hand, the Vgg = -0.5V have values of positive polarities in terms of the drain current and keeps increasing as the voltage increases.  On the last simulation, I have seen that as the voltage of the gate increases, the drain current meter reading across the resistor decreases wherein it has an indirect relationship that if the gate voltage decreases, the drain current will increase. CONCLUSION In a JFET, the current was never pinched off totally but it reached a saturation level instead. As the drain bias starts to increase, the device will start to pinch off near the drain end of the gate. This response will also increase the resistance as a larger depletion zone was growing and at a time it reached a point where the resistance of JFET reached its maximum value. In this experiment, I have learned that JFET have certain characteristics depending on its biasing. In the zero gate bias, the drain characteristic is that the current keeps increasing especially if the resistance is in maximum value while if the gate is biased, it affects the drain current reading making the current to drop or it reads no current at all but based on what I read the current cannot be zero even the resistance was large, maybe it is what we call as the parallax/reading error of the multimeter which is possible to happen in any experiment.