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ECE241 cheat sheet, Schemes and Mind Maps of Algebra

Koya University (Kurdistan Region) (KU)Algebra

BOOLEAN ALGEBRA. 5a. x · 0 = 0 5b. x + 1 = 1. 6a. x · 1 = x 6b. x + 0 = x ... in simulation you can see any logic signal, not just input and output.

Typology: Schemes and Mind Maps

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!
OTHER FLIP FLOPS AND REGISTERS
BOOLEAN ALGEBRA
5a. x · 0 = 0 5b. x + 1 = 1
6a. x · 1 = x 6b. x + 0 = x
7a. x · x = x 7b. x + x = x
8a. x · x
! = 0 8b. x + x
! = 1
9. !x
! = x
10a. !x · y = y · x10b. !x + y = y + x commutative
11a. !x · (y · z) = (x · y) · z 11b. !x + (y + z) = (x + y) + z
12a. !x · (y + z) = x · y + x · z 12b. !x + y · z = (x + y) · (x + z)associative
13a. !x + x · y = x 13b. !x · (x + y) = x absorption
14a. !x · y + x · y
! = x 14b. !(x + y) · (x + y
!) = x combining
15a. !x · y = x
! + y
! 15b. !x + y = x
! · y
!DeMorgan’s
16a. !x + x
! · y = x + y 16b. !x · (x
! + y) = x · y covering
17a. !xy + yz + x
!z = xy + x
!z 17b. !(x + y)(y + z)(x
! + z) = (x + y)(x
! + z)
GATES AND LATCHES
ADDERS
ECE241 MIDTERM
ripple carry adder
BASIC (SR) LATCH
CAUTION: When S = R = 1 then S = R = 0, oscillation occurs
GATED SR LATCH
XOR
High on odd values of 1
MUX
NAND
NOR
XOR = xy" + yx"#
XNOR = xy + x"y"
GATED D LATCH / D FLIP FLOP
NEG EDGE TRIGGERED D FLIP FLOP
master slave D flip flop
POS EDGE TRIGGERED D FLIP FLOP
Use NOR gates to construct
neg edge triggered gate
level / pos / neg triggered
jk flip flop
4 bit right shift register
t flip flop
4 bit parallel load shift register
vlib: set the working directory, where all the compiled
Verilog goes, use vlib work#
$#
vlog: compiles Verilog modules to working directory, use
vlog <filename>.v$#
vsim: starts vsim simulator, use vsim <filename>$#
log 2 signals: log {SigA, SigB}$#
add a wave to show two signals: add wave {SigA, SigB}$#
DE1_SoC.qsf file: maps port names in top-level module to
pin numbers in the FPGA chip$#
FPGA: Field Programmable Gate Array, a prog. device for
implementing digital circuits$#
latch is level sensitive, flip flop is edge-sensitive$#
Why is simulation important?!
•shows design works before implementation$#
•makes debugging easier and faster$#
•in simulation you can see any logic signal, not just
input and output$#
•you can see responses that cannot be observed in
hardware$
mod sim
anais poirier
pf2
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OTHER FLIP FLOPS AND REGISTERS

BOOLEAN ALGEBRA

5 a. x · 0 = 0 5 b. x + 1 = 1 6 a. x · 1 = x 6 b. x + 0 = x 7 a. x · x = x 7 b. x + x = x 8 a. x · x̅ = 0 8 b. x + x̅ = 1

9.! x̅ = x 10 a. x · y = y · x 10 b. x + y = y + x commutative 11 a. x · (y · z ) = ( x · y ) · z 11 b. x + ( y + z ) = ( x + y ) + z 12 a. x · ( y + z ) = x · y + x · z 12 b. x + y · z = ( x + y ) · ( x + z ) associative 13 a. x + x · y = x 13 b. x · ( x + y ) = x absorption 14 a. x · y + x · y̅ = x 14 b. ( x + y ) · ( x + y̅ ) = x combining 15 a. x · y = x̅ + y̅ 15 b. x + y = x̅ · y̅ DeMorgan’s 16 a. x + x̅ · y = x + y 16 b. x · ( x̅ + y ) = x · y covering 17 a. xy + yz + x̅z = xy + x̅z 17 b. ( x + y )( y + z )( x̅ + z ) = ( x + y )( x̅ + z )

GATES AND LATCHES

ADDERS

ECE241 MIDTERM

half adder

full adder

ripple carry adder

BASIC (SR) LATCH CAUTION: When S = R = 1 then S = R = 0, oscillation occurs GATED SR LATCH XOR High on odd values of 1 MUX NAND NOR XOR = xy̅ + yx̅ XNOR = xy + x̅y̅ GATED D LATCH / D FLIP FLOP NEG EDGE TRIGGERED D FLIP FLOP master slave D flip flop POS EDGE TRIGGERED D FLIP FLOP Use NOR gates to construct neg edge triggered gate

level / pos / neg triggered

jk flip flop

4 bit right shift register

t flip flop

4 bit parallel load shift register

vlib: set the working directory, where all the compiled Verilog goes, use vlib work vlog: compiles Verilog modules to working directory, use vlog .v vsim: starts vsim simulator, use vsim log 2 signals: log {SigA, SigB} add a wave to show two signals: add wave {SigA, SigB} DE1_SoC.qsf file: maps port names in top-level module to pin numbers in the FPGA chip FPGA: Field Programmable Gate Array, a prog. device for implementing digital circuits latch is level sensitive, flip flop is edge-sensitive Why is simulation important?

  • • shows design works before implementationmakes debugging easier and faster
  • in simulation you can see any logic signal, not just
  • input and outputyou can see responses that cannot be observed in hardware

mod sim

anais poirier

module mux2to1(x, y, s, m); input x; //select 0 input y; //select 1 input s; //select signal output m; //output //assign m = s & y | ~s & x; // OR assign m = s? y : x; endmodule

mux2to

module ShiftReg( input [3:0] D, input Clock, Resetn, Loadn, output SerialOut); reg [3:0] Q; always @(posedge Clock) if (!Resetn) Q <= 0; else if (!Loadn) Q <= D; else begin Q[0] <= 1'b1; Q[1] <= Q[0]; Q[2] <= Q[1]; Q[3] <= Q[2]; end assign SerialOut = Q[3]; endmodule

shift register

module add8( input [7:0] A, input [7:0] B, output [7:0] Sum, output Cout); assign {Cout, Sum} = A+B; endmodule

add 8

module adder(A, B, S, cin, cout); input [2:0] A, B; input cin; output [2:0] Sum; output cout; wire [1:0] f_cout; full_adder F0( .ci(cin), .a(A[0]), .b(B[0]), .s(S[0]), .co(f_cout[0]) ); full_adder F0( .ci(f_cout[0]), .a(A[1]), .b(B[1]), .s(S[1]), .co(f_cout[0]) ); full_adder F0( .ci(f_cout[1]), .a(A[2]), .b(B[2]), .s(S[2]), .co(f_cout[0]) ); endmodule module reg4bit (D, Clock, Resetb, Enable, Q); input [3:0] D; input Clock, Resetb, Enable; output reg [3:0] Q; always @(posedge Clock) if (!Resetb) Q <= 0; else if (Enable) Q <= D; endmodule

4 bit register

3 bit add

module FunctionSelect(input [3:0] X, Y, input [2:0] Sel, output reg [3:0] Fout); wire [3:0] w1, w2; ModA U1(.X(X), .Y(Y), .ModAout(w1)); ModB U2(.X(X), .Y(Y), .ModBout(w2)); always @(*) case (Sel) 3'b000: Fout = w1; 3'b001: Fout = ~X; 3'b010: Fout = {X[3:2],Y[1:0]}; 3'b011: Fout = w2; 3'b100: Fout = ~(X & Y); default: Fout = 3'b000; endcase // case (Sel) endmodule // FunctionSelect

function select

vlib work vlog mux.v vsim mux log {/} add wave {/} #signal names need to be in {} brackets force {SW[0]} 0 force {SW[1]} 0 force {SW[9]} 0 run 10ns

.do