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John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 1
EE 579: Digital System Testing
Lecture 1: Course Introduction and Overview
EECS 579 Course Goals
To learn about
- The role of testing in digital systems
- The various types of faults expected and how to model them
- Testing methods and how to compute tests for manufacturing and field testing
- Design methods to improve testability
- Built-in self-test (BIST) methods
- Relation to the design verification problem
To gain project experience in one of the following:
- Research
- Using/building CAD tools for testing
- Testing VLSI chips
John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 3
Course Organization
Class Schedule Tuesday and Thursday 9:10 – 10:30 am EWRE Building, Room 153 Instructor's TBA Office Hours Location: EECS Building, Room 2114e Contacting the See him in person during the above office hours or Instructor Send e-mail to [email protected] or Telephone 763- Prerequisites : Course in Logic Design such as EECS 270, Basic architecture and programming (C/C++) Text (required) : Essentials of Electronic Testing by M. Bushnell & V. Agrawal, Kluwer, 2000. Additional books will be placed on reserve in the Media Union Library. Lecture notes and other material will be posted on the class home page http://www.eecs.umich.edu/courses/eecs579/
Tentative Course Plan
- Introduction Chap. 1 - 3
- Fault modeling Chap. 4
- Combinational circuit testing Chap. 7
- Sequential circuit testing Chap. 8
- System testing Chap. 9 Midterm Exam
- Design for testability Chap. 6, 14
- Built-in self-testing Chap. 15
- Fault simulation Chap. 5
- System-on-a-chip (SOC) issues Chap. 18
- Other topics TBA Project Presentations Final Exam
John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 7
Why Do Systems Fail?
- Human design errors
- Manufacturing defects: IC processing and packaging;
- Subsystem assembly and wiring
- Installation errors
- Operational (field) failures:
- Environment: temperature, humidity, vibration
- Power supply
- Interference: ESD, EMI, RFI, radioactivity
- Wear and tear: friction, corrosion, electromigration
- Human operator errors
Horror Story 1: World War III (almost)
John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 9
Horror Story 2: Three-Mile Island
- How to make a nuclear reactor safe Remove fuel rods from reactor core (normal) Low-pressure cooling system 1 (normal) Low-pressure cooling system 2 (normal backup) High-pressure cooling system 3 (emergency) Blow pressure release plugs and flood containment building (extreme emergency) Meltdown
- Why the accident happened: Minor hardware faults occurred while cooling system 1 was shut down for routine maintenance Major design errors Extreme operator errors
Horror Story 3: Therac-
- One of the best-documented computer accidents
- Therac-25 was a radiation machine for cancer therapy
- It generated X-rays of programmable intensity and duration
- It caused a mysterious and deadly series of accidents in the mid 1980s Operator set correct therapeutic dose levels Some patients received high and deadly doses of radiation Initial attempts to reproduce the accident conditions failed
- Why the accident happened: Primary reason: Faulty software in the form of a badly designed interface timing loop Secondary reasons: Absence of hardware interlocks Reuse of old, undocumented (assembly language) code
John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 13
Why is Testing Important?
(Why do we need a class in testing?)
- Faults cannot be eliminated entirely
- Safety and reliability Its usually not OK to sell faulty products Digital systems are the “brains” of embedded systems In many applications, undetected failures are dangerous
- Testing is inherently a hard problem Good progress has been made, but systems keep getting more complex
- Testing is very expensive ATE for IC production costs millions of dollars Test development affects time to market Adding circuits to improve testability can be costly
Why Testing is Hard
- IC technology is a moving target
- Clock rates and power consumption are soaring too
1960 1970 1980 1990 2000
Number of transistors per IC 1
2
3
4
5
6
7
8 32-bit microprocessorMillion-transistor
DRAM1G-bit
9 First commercialintegrated circuit (a flip-flop)
microprocessorFirst (four-bit)
1K-bitDRAM
1M-bitDRAM
10
10
10
10
10
10
10
1
10
10
John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 15
Why Testing is Hard: SOCs
- SOCs incorporate multiple complex devices and/or technologies on a single IC Processors Memories Communication circuits Application-specific circuits
- In the future: FPGAs MEMS
Testing Costs
- Manufacturing test equipment Capital cost of automatic test equipment (ATE) Operating cost of test facility
- Test software development Automatic test pattern generation (ATPG) code Fault simulation and other debugging code
- Design for testability (DFT) Chip area overhead (implying yield loss) Performance overhead
John P. Hayes University of Michigan EECS 579 Fall 2001 Lecture 01: Page 19
Automatic Test Equipment
Advantest T
Testing Costs: DFT
Intel Pentium Microprocessor
- Data from Keynote Address, International Test Conference 1995
- Cost impact of BIST logic that increases area by 1 or 15%
Nominal Pentium die
1% Die size increase
15% Die size increase Wafer cost $1,460 $1,460 $1, Die size 160.2mm 2 161.8mm 2 184.2mm 2 Die cost $84.06 $85.33 $102. Added annual cost — $63.5M $961M Dies required/week 1M 1M 1M Chips fabricated/week 498.1K 482.9K 337.5K
