EEE 120 MIDTERM EXAM WITH COMPLETE SOLUTION 2026-2027!!, Exams of Engineering

EEE 120 MIDTERM EXAM WITH COMPLETE SOLUTION 2026-2027!!...

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EEE 120 MIDTERM EXAM WITH COMPLETE SOLUTION 2026-2027!! Most digital circuits represent binary values using OV and +5 V LOW (or binary 0) in a digital system typically corresponds to ov The Low edge of a digital clock occurs when the signal changes from HIGH to LOW What is the frequency of a clock waveform whose period is 50 microseconds 20 kHz The Boolean equation for an OR gate is AtB=X Waveforms A and B represent the inputs to an AND gate. During which time interval will the output from the gate (X) be HIGH? time interval 2 If both inputs of an OR gate are normally HIGH but one of them momentarily dips LOW, the output will stay HIGH The Boolean equation for a NAND function is X = (AB) Which logic function can be implemented by connecting an inverter to the output of an AND gate? NAND Which logic function can be implemented by connecting an inverter to the output of a NOR gate? OR What are you not allowed to do when building digital logic circuits? (Multiple correct answers are possible. Wrong answers will deduct points. Connect multiple outputs of different gates. Connect an output of a logic gate to twelve inputs of different gates. T/F You can construct an XOR gate using only AND/OR/NOT gate(s)? true Which gate can be used to generate a true output if an odd number of inputs is true? XOR T/F: An NAND gate with inverters connected to each input behaves like AND gate False What is the period of a clock waveform whose frequency is 4 mHz? 250s Waveforms A and B represent the inputs to an AND gate. During which time interval(s) will the output from the gate (X) be HIGH? none will be high Which logic function is represented by the equation ABCD = X? AND If one input of an OR gate is HIGH while the other is a clock signal, the output is HIGH Which logic gate is described by the following truth table? XNOR T/F: In Boolean algebra, 1-0=0 True To change a 3-input NOR gate into a 3-input AND gate would require: Three inverters The least number of gates that could be used to build logic circuit with the Boolean expression (A+B)’C would be. Note: do not worry about what is available in the hardware labs. 2 Which rule of Boolean algebra does the example shown below represent? A1=A X=(A+B)(C +D) The final output of a sum-of-products (SOP) circuit is generated by anOR How many NAND gates does it take to make an AND gate? 2 Which term is missing from below expression to have it written in Standard or Canonical SOP Form: F = A'BC + ABC + A'B'C'+ AB ABC’ When you write the output equation for a function in POS, you look for places where the truth table output is: 0 Which Boolean equation results from this Karnaugh Map? X= B'D'+A'C'+A'BD+BC'D+AB'C+ACD" Which Boolean equation results from this Karnaugh Map? A'D+BD+A'BC'+AB'C'D* Which Boolean equation results from this Karnaugh Map? ACD'+B'CD'+C'D Find the Min POS for the following 4-variable function: (A+ B'+D) (B+D') Which binary value equals 24-2? 0000.0100 The decimal equivalent of binary 0010111 is 23 Convert decimal 58 to binary 00111010 The hexadecimal equivalent of decimal 60 is 3c The range of positive numbers possible in an eight-bit two's complement system is 0 to 127 How is -32 represented in eight-bit two's complement notation? 11100000 When using signed two's complement notation, what is the decimal value of 11101100? -20 Solve this binary problem: 01100100 + 00000101 01101001 Add the following hexadecimal numbers: FA + C8 102 Subtract the following Hexadecimal numbers: F8 - C2 36 Convert the following decimal number to binary: 59.75 111011.11 Convert the following binary number to hexadecimal: 111011.11 3B.C What is the decimal value of the 4-bit 2's complement number 1011? -5 Convert the following hexadecimal number "38" to Octal: 070 Convert the following binary number "0010111" to Octal 027 Convert the following decimal number to Hexadecimal: 27 1B For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is: a one will be added to the final result What is the major difference between half-adders and full-adders? Full adders have a carry input capability.