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Examination Instructions for BEng (Hons) Mechanical Engineering Unit 64EE1051: Electronics, Exams of Electrical Engineering

Manchester Metropolitan University (MMU)Electrical Engineering

The instructions for an exam held at the manchester metropolitan university in 1999/2000 for the beng (hons) mechanical engineering unit 64ee1051: electronics. The exam covers topics such as operational amplifiers, differentiators, logic gates, and designing a logic circuit for an alarm system. Candidates are required to answer any three questions, which include drawing circuits, deriving expressions, sketching waveforms, and minimizing functions.

Typology: Exams

2010/2011

Uploaded on 10/06/2011

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S522 02/09/02
THE MANCHESTER METROPOLITAN UNIVERSITY
FACULTY OF SCIENCE AND ENGINEERING
DEPARTMENT OF ENGINEERING AND TECHNOLOGY
SESSION 1999/2000
Examination for the
BEng (Hons) MECHANICAL ENGINEERING
UNIT 64EE1051 : ELECTRONICS
Friday 19 May 2000
9.30 am to 11.30 am
Instructions to Candidates
Answer any THREE questions.
pf3

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S522 02/09/

THE MANCHESTER METROPOLITAN UNIVERSITY

FACULTY OF SCIENCE AND ENGINEERING

DEPARTMENT OF ENGINEERING AND TECHNOLOGY

SESSION 1999/

Examination for the BEng (Hons) MECHANICAL ENGINEERING

UNIT 64EE1051 : ELECTRONICS

Friday 19 May 2000

9.30 am to 11.30 am

Instructions to Candidates

Answer any THREE questions.

02/09/02 continued

  1. (a) Draw the circuit of an operational amplifier-based inverting amplifier and derive an expression for its voltage gain. [15]

(b) Show how the circuit in (a) can be modified to sum two input voltages, and write down an expression for the output voltage in terms of the inputs and the circuit components. [10]

  1. (a) Draw the circuit of a differentiator using an ideal operational amplifier and derive an expression for it’s output voltage in terms of the circuit components and the input voltage of the circuit. [17]

(b) Sketch the output waveform for the input waveform shown below.

[8]

  1. (a) What do you understand by the following terms as applied to logic gates?

(i) CMOS (ii) TTL (iii) Fan-out (iv) Noise margin (v) LS as in 74LS [10] (b) Minimise, using a Karnaugh map, the function:

F = A. B.C.D + A. B. C.D + A. B.C.D + A. B.C.D [12]

(c) Realise the above minimised expression using any logic gates. [3]

voltage

t (^1) t 2 time