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embedded systems practical.pdf
Typology: Lecture notes
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Sr No Title
Introduction Introduction to Embedded System Practical Introduction to 8051 Microcontroller Introduction to TKBase Trainer kit
List of Practical
Interrupt handler / controller: Interrupt handling mechanism handles multiple interrupts generated from various processes simultaneously. There can be number of interrupt sources or group of sources. The service to these sources can have priorities according to the system priorities. Certain sources of interrupts are non maskable and cannot be disabled.
There is a separate program and data memory for the controller. Internal and external RAM for registers, temporary data and stack, Internal and external ROM for program memory, internal flash memory, memory cards, memory buffers of ports, cache memories. Communication ports: several communication ports serial as well as parallel to communicate with various peripheral devices like keyboards touch screens, sensors, transducers etc. (input) or printers, LED / LCD display, network etc. (output).
Power supply, Reset and Oscillator Circuit: Many embedded systems have their own power supply; however fee systems use PC power by connecting to computer. Power supply has range of voltages in one of following range 5 ±0.25V, 3.3 ±0.3V, 2 ±0.2V and 1.5 ±0.2V Reset circuit helps the processor to begin processing of instructions from a starting address. This address is set by default in processor Program Counter (PC) on a power up. A program to be executed after reset is - a system program which executes from beginning, or a boot program, or a system initialization program. Reset circuit activates for a fixed period and then deactivates.
Software components of embedded system -
An embedded system processor executes software that is specific to a given application system. Software components include editor, assembler, linker, and loader. The steps involved in executing an embedded assembly program are as followed –
Fig 2 Process of converting assembly language program into the machine codes and obtaining the ROM image
Software is developed in higher level languages to save efforts instead of using assembly language. Following are different program layers in embedded C
Processor commands Main Function Interrupt service Routines Tasks 1 ….. N Kernel and scheduler Standard Library functions
Fig 3 Program Layers in embedded C
Machine specific Assembly language program
From library needed machine codes
Machine codes for the programs at various addresses
Bytes for linked programs
Data Bytes
Machine codes ready for locating at various addresses
Device (ROM) programmer (burner)
Embedded System ROM Memory
Assembler
Linker Loader
Re allocating addresses
Introduction to 8051 Microcontroller
8051 architecture
8051 architecture consists of 8 bit CPU with processing capability, oscillator driver unit, 4k on chip program memory, 128 bytes internal data memory, 128 bytes of SFR, 32 general purpose I/O lines organized into 4 8-bit bidirectional ports, two 16 bit timer units and a full duplex programmable UART (Universal Asynchronous Receiver Transmitter) for serial data transmission.
Fig below shows the internal architecture of 8051 microcontroller
Fig 5 (A) Pin configuration and (B) Internal architecture of 8051 microcontroller
8051 memory organization
8051 is build around Harvard architecture. Program and data memory is separated logically. Separate address spaces are assigned for program and data memory. 8051‟s address bus is 16 bit wide and it can address up to 64KB memory.
Program or code memory is lowest 4K bytes of program memory as on chip memory (built in chip memory). Internal and external program memory is switched
means instructions are to be executed from the program memory up to 4K and logic 0 on this pin means that chip is in external program execution mode. The
Enable). This is not activated for internal program memory.
Basic 8051 architecture supports 128 bytes of internal data memory and 128 bytes of special function register memory. SFR is not available for the user for general data memory operation. The address range of internal user data memory is 00 H to 7F H. SFR reside at memory area 80 H to FF H. control signals used for external
accessed is Data Pointer (DPTR). DPTR is made up of two 8 bit registers DPH and DPL. This register is accessible to the user and its contents can be modified. In external data memory operations port 0 emits the contents of DPL and port2 emits the contents of DPH.
Internal data memory addresses are always one byte long. It can accommodate up to 256 bytes of internal data memory (Ranging from 0 to 255). 8051 uses Direct addressing of data memory greater than 7F H
Fig 6 Memory organization of 8051
8051 registers: 8051 registers can be broadly classified as CPU registers and scratchpad registers. CPU registers: Accumulator B register Program Status word
The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for the Timer 0 as for Timer 1. Substitute TR0, TF0, and INT0 for the corresponding Timer 1 signals in Figure 2. There are two different GATE bits, one for Timer1 (TMOD.7) and one for Timer 0 (TMOD.3).
Figure 8. Timer/Counter 0/1 Control (TCON) Register
Mode 1 Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.
Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload.
Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.
Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 7. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, and TF0, as well as the INT0 pin. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt
Fig 10 Four 7 segment display characters.
Fig 11 using 7 segment to display output Hex Keypad
8051RD2 signal pins from pin 1 through 40 are made available to the users from IO header CN5 from pin marked 1 through 40. The first 8 pins of CN5 are mapped to first 8 pins of 8051RD2. 16 hex keypad is interfaced to 8051RD2 as matrix of 4 scan signals and 4 return signals. Pressing a key switch push button generates a logic Low on the associated RD2 pin.
Fig 12 Hex Keypad Thus, 4 X 4 keyboard matrix, giving a total of 16 keys with each key representing a single hexadecimal value as shown in Fig 12. The 8051RD2 microcontroller program scans keyboard matrix to detect which key was pressed. After detection, corresponding hex code is displayed on the 4 character 7 segment display. P1.0 to P1.3 are assigned as output (key scan) and P1.4 to P1.7 are assigned as inputs (key returns). User program detects which key has been pressed while a lookup table defines the value of each key.
RS232C Serial Port
RS232 signals are used to implement the interface (RD and TD signals). RS transmit and receive signals appear on the male DB9 connector labeled SER-D9. The user provides RS232 UART code. A standard serial cable can be used to connect the 8051RD2 with the PC. A standard MAX232 RS232 is used to drive RX and TX signals. Fig 13 shows the connection between the Serial port and DB9connector, including the MAX232 RS-232 voltage converter. A jumper is placed between RX TX pin for an easy loopback test.
Fig 13 Connection using the DB9 connector.
Introduction to Development Environment
Software Used Execution of Embedded C program is done in two steps. First step is performed at the host machine. Here, a C program is compiled and built to generate a hex file, which is assembly code generated by a tool. Several compilers are available for compiling and linking program. Following are few examples –
Crossware Tools for Embedded Development μVision 5
1. Crossware Tool
Steps to be followed – Generation of hex file in crossware
Fig 15 Crossware C compiler IDE
Fig 16 new dialog box.
Fig 17 Target Selection
Fig 20 Program file format
Fig 21 Final step in creation of project
Fig 22 Crossware IDE
10.Write the embedded c program in the main.c, which is open in the editor window. Save the file. Compile to create object file.
Simulation of the program
Project / workspace window
Editor window
Output Window