Exam 2 Booster - Embedded System Problems | CSCE 313, Exams of Computer Science

Material Type: Exam; Class: EMBEDDED SYSTEMS; Subject: Computer Science & Engineering; University: University of South Carolina - Columbia; Term: Spring 2004;

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CSCE 313 – Spring 2004 - Exam#2 “Booster”: Dr. James P. Davis Page 1 of 4
CSCE 313 – Spring 2004 _______________________
Exam #2 “Booster: Name
_______________________
Name
I/O Interfacing and Memory Mapped I/O: Our focus on this Booster exam is on the principles of interfacing
and programming the 68K microprocessor to interface with the outside world. We have discussed the basic
interface circuitry, the integration of circuitry with the 68K processor and bus architectures, the mechanisms of
how this interfacing works, and the programming of I/O devices through such interfaces. This is an exam where
you are required to think in terms of the design of an embedded system. Use of the course text is permitted.
Instructions: This Take Home exam is to be completed by a Lab Team, and is not to be discussed among
members of different teams. The programming problems are to be entered into WISM68 and program listing
files are to be turned in for those problems where it is needed. There are 3 problems, two of which involve
writing programs.
Problem 1 (25 points): Memory Mapped I/O: We
have the following address decoding circuit that allows
us to access an I/O device at one specific memory
address. We have the address lines A1-A23, AS(low)
and LDS(low) entering the circuit, and SEL(low) leaving
the device; the DTACK(low) control signal is also pulled
off the value of SEL(low). At this point, the actual I/O
device doesn’t matter.
1a (9 pts): What is the address of the location in
memory that is put on the Address Bus in order to allow
a 68K program to read/write to this device?
______________________
1b (8 pts): In this circuit, what purpose does the
SEL(low) signal serve, i.e., if set “true”, what effect
does it have?
___________________________
___________________________
1c (8 pts): In this circuit, what purpose does the
DTACK(low) signal serve, i.e., what does it signify?
___________________________
___________________________
Mapped I/O Addressing Circuit
(Antonakos, 2
nd
ed., 1999)
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CSCE 313 – Spring 2004 _______________________

Exam #2 “Booster: Name

_______________________

Name

I/O Interfacing and Memory Mapped I/O : Our focus on this Booster exam is on the principles of interfacing and programming the 68K microprocessor to interface with the outside world. We have discussed the basic interface circuitry, the integration of circuitry with the 68K processor and bus architectures, the mechanisms of how this interfacing works, and the programming of I/O devices through such interfaces. This is an exam where you are required to think in terms of the design of an embedded system. Use of the course text is permitted.

Instructions: This Take Home exam is to be completed by a Lab Team, and is not to be discussed among members of different teams. The programming problems are to be entered into WISM68 and program listing files are to be turned in for those problems where it is needed. There are 3 problems, two of which involve writing programs.

Problem 1 (25 points): Memory Mapped I/O : We have the following address decoding circuit that allows us to access an I/O device at one specific memory address. We have the address lines A1-A23, AS(low) and LDS(low) entering the circuit, and SEL(low) leaving the device; the DTACK(low) control signal is also pulled off the value of SEL(low). At this point, the actual I/O device doesn’t matter.

1a (9 pts): What is the address of the location in memory that is put on the Address Bus in order to allow a 68K program to read/write to this device?

______________________

1b (8 pts): In this circuit, what purpose does the SEL(low) signal serve, i.e., if set “true”, what effect does it have?

___________________________

___________________________

1c (8 pts): In this circuit, what purpose does the DTACK(low) signal serve, i.e., what does it signify?

___________________________

___________________________

Mapped I/O Addressing Circuit (Antonakos, 2 nd^ ed., 1999)

Problem 2 (25 pts): I/O Device Programming : We have the I/O device as shown in the figure below, which is different from problems #1 & 2. It has a base address of $E00001, and allows writing of an eight character message to the display. Each character LED is available on odd addresses starting at the base address of the I/O device, and we are writing a byte to that location to output to the LED using the circuit shown. Here’s some requirements for your program: (1) start your program at $8100 (done below), (2) start your data at $8000 (done below), (3) put the string ‘MY 68000’ in your data area, (4) to move data to the various memory addresses for writing the string’s ASCI characters to the LEDs, you’ll write the characters from right to left, so you’ll start at the highest address where the string characters are stored and work your way downward from the last to the first character, (5) you’ll have a control loop to manage the writing of the characters of the string to the 8 addresses of the LED display device, so make sure you start from the correct address (given point 4) and iterate your loop for each subsequent character, make sure you properly adjust your counter to account for the byte locations for each LED being mapped to odd addresses in 68K memory.

Type/write your 68K program instruction sequence in here to write the 8-character string ‘MY 68000’ to the character LEDs. Use the back of the page to design your program if you need the space. Please write legibly!

**** 3a. Data Space here ************

ORG $

MSG

**** 3b. Program Space here*********

ORG $

DISP

RTS

ASCII Character LED Display I/O Device (Antonakos, 2nd^ ed., 1999)

PE Memory Words

Command and Status Words 2

(^16) Locations = 64K

Base Address for Location of Input Data Written by 68000.

Base Address for Location of Output Data to be Read by 68000.

Addresses and Sizes Passed in via Command Words

Input Data Address (2 16 locations)

Output Data Address (2^16 locations)

31 0

31 16 15 0

Output Data Size (2 13 locations = 8K chunk)

Input Data Size (2 13 locations = 8K chunk) 31 19 18 65 3 0 Go/Clear bit (set by Host) Busy bit (set by PE) Done bit (set by PE) Opcode bits (set by Host)

5 3

Mode bit (set by Host) = 1

Opcode bits (set by Host)

68000 Base Address = $CE

Byte 3 Byte 2 Byte 1 Byte 0

Byte 3 Byte 2 Byte 1 Byte 0

Source: Davis & Choudary, 2002.

******* ISR Routine to write 32-bytes to PE *********** WRITEBUF ORG $ PE_BASE ORG $CE ORG $ LOADIT

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RTE

******* ISR Routine to read 16-bytes from PE *********** READBUF ORG $ 6000 PE_BASE ORG $CE ORG $ DUMPIT

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RTE

3a: Write ISR routine to write 32 bytes to the PE device, initiate the command sequence and start execution, and then return. 3b: Write ISR to read 8 bytes from the PE device’s memory on interrupt. 3c: The addresses written into the Exception Vector table for: (1) Trap #4 (to write and go) = _$___________________ and (2) Level 5 Interrupt Autovector (to clear and read from PE) = $_____________________________.