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Associate Practice Exam
Question 1. Which university was the original birthplace of the RISC‑V ISA? A) MIT B) Stanford University C) University of California, Berkeley D) Carnegie Mellon University Answer: C Explanation: RISC‑V was created at UC Berkeley in 2010 as an open‑source instruction set architecture. Question 2. The primary philosophical difference between RISC‑V and proprietary ISAs such as ARM is that RISC‑V is: A) Faster in all workloads B) Open and royalty‑free C) Only 64‑bit D) Designed exclusively for GPUs Answer: B Explanation: RISC‑V’s “free and open” nature means anyone can use the ISA without licensing fees, unlike proprietary ISAs. Question 3. Which organization is responsible for the governance and ratification of new RISC‑V extensions? A) IEEE B) RISC‑V International C) Linux Foundation D) ISO Answer: B
Associate Practice Exam
Explanation: RISC‑V International, a non‑profit, manages the specification development and extension ratification process. Question 4. In the RISC‑V community, a “member” that contributes to the specification but does not have voting rights is called a: A) Affiliate B) Contributor C) Associate member D) Observer Answer: D Explanation: Observers can view and comment on drafts but do not have voting rights. Question 5. The “RISC‑V Green Card” is best described as: A) A hardware debugging tool B) A 2‑page reference sheet of the ISA C) An emulator for RISC‑V cores D) A certification exam guide Answer: B Explanation: The Green Card is a concise reference card summarizing instruction encodings and CSR fields. Question 6. Which of the following is NOT a standard RISC‑V specification document? A) Unprivileged ISA Manual B) Privileged ISA Manual C) Vector Extension Manual D) Intel Architecture Manual
Associate Practice Exam
Explanation: RV32E reduces the register file to 16 registers to save area in tiny embedded devices. Question 10. Which instruction format contains a 12‑bit signed immediate and a 5‑bit destination register? A) R‑type B) I‑type C) S‑type D) U‑type Answer: B Explanation: I‑type instructions encode a 12‑bit immediate and rd field. Question 11. In a RISC‑V R‑type instruction, the funct7 field occupies which bits? A[31:25] B[24:20] C[19:15] D[11:7] Answer: A Explanation: Bits 31‑25 hold funct7, used for differentiating similar opcodes. Question 12. The “M” extension adds which capabilities to the base ISA? A) Multiply and divide integer operations B) Memory‑mapped I/O C) Machine‑mode only instructions D) Multimedia extensions
Associate Practice Exam
Answer: A Explanation: The M extension supplies integer multiplication (MUL, MULH) and division (DIV, REM). Question 13. Which of the following is a valid atomic instruction introduced by the “A” extension? A) lr.w B) amoswap.d C) sc.h D) All of the above Answer: D Explanation: The A extension defines load‑reserved/store‑conditional (lr/sc) and atomic memory‑operation (amo) instructions. Question 14. The “F” extension provides which type of operations? A) Fixed‑point arithmetic B) Single‑precision floating‑point C) Fast integer multiplication D) Fault tolerance Answer: B Explanation: The F extension adds IEEE‑754 single‑precision floating‑point instructions. Question 15. The “D” extension adds support for: A) Double‑precision floating‑point B) Debugging facilities C) Deterministic execution
Associate Practice Exam
C) Machine mode (M) D) Hypervisor mode (H) Answer: C Explanation: Machine mode is the most privileged and is required for boot and low‑level control. Question 19. The CSR named mstatus is primarily used to: A) Store the program counter on exception B) Control interrupt enable bits and privilege level C) Hold the address of the trap handler D) Provide a timestamp counter Answer: B Explanation: mstatus holds global interrupt enable flags, previous privilege level, and other status bits. Question 20. When an exception occurs, the address of the faulting instruction is saved in which CSR? A) mtvec B) mepc C) mcause D) mip Answer: B Explanation: mepc stores the program counter of the instruction that caused the trap. Question 21. Which CSR holds the vector base address for machine‑mode exception handling?
Associate Practice Exam
A) mtvec B) mscratch C) mie D) medeleg Answer: A Explanation: mtvec contains the base address (and mode) of the trap vector. Question 22. In RISC‑V, the interrupt enable bit for external interrupts in machine mode is located in which register? A) mstatus B) mie C) mip D) mtval Answer: B Explanation: mie contains individual enable bits for various interrupt sources. Question 23. Which of the following memory ordering models does RISC‑V define for atomic operations? A) Sequential consistency only B) Release‑acquire semantics C) Weak ordering with fences only D) No ordering guarantees Answer: B Explanation: RISC‑V defines acquire, release, and acquire‑release semantics for atomic instructions and provides fence instructions for stronger ordering.
Associate Practice Exam
Question 27. Which directive tells the assembler to place following code into the text (executable) segment? A) .data B) .bss C) .text D) .align Answer: C Explanation: .text switches the current section to the executable code segment. Question 28. The pseudo‑instruction li rd, imm may expand to which actual instruction(s) when the immediate does not fit in 12 bits? A) addi only B) lui followed by addi C) ori only D) lui only Answer: B Explanation: li loads a 32‑bit immediate using lui (upper 20 bits) and addi (lower 12 bits) when needed. Question 29. In RISC‑V assembly, the label loop: is typically used for: A) Defining a data variable B) Marking a branch target C) Declaring a macro D) Setting a system call number Answer: B
Associate Practice Exam
Explanation: Labels identify addresses that can be the target of branch or jump instructions. Question 30. Which instruction implements an unconditional jump to a label? A) beq x0, x0, label B) jal x0, label C) jal ra, label D) j label Answer: C Explanation: jal ra, label jumps to the label and stores the return address in ra. (Option B would jump without saving return address, but commonly jal is used with ra.) Question 31. The pseudo‑instruction mv rd, rs expands to which real instruction? A) add rd, rs, x B) sub rd, rs, x C) xor rd, rs, x D) or rd, rs, x Answer: A Explanation: mv is an alias for add rd, rs, x0, copying the source register. Question 32. Which of the following correctly loads a byte from memory address contained in s1 into a0? A) lb a0, 0(s1) B) lw a0, 0(s1) C) lbu a0, 0(s1) D) Both A and C are valid, but C loads unsigned
Associate Practice Exam
B) 25 %
C) 40 %
D) 60 %
Answer: B Explanation: The 16‑bit compressed instructions often cut code size by about a quarter on average. Question 36. In a 5‑stage pipeline (IF‑ID‑EX‑MEM‑WB), a taken branch causes a penalty of: A) 0 cycles (branch prediction) B) 1 cycle C) 2 cycles D) 3 cycles Answer: C Explanation: Without branch prediction, the pipeline must flush the two instructions fetched after the branch, incurring a two‑cycle penalty. Question 37. Which GCC flag enables generation of RISC‑V code with the “C” extension? A) - march=rv32ic B) - march=rv32i_c C) - march=rv32imac D) - march=rv32ic - mabi=ilp32d Answer: A Explanation: - march=rv32ic selects the base integer ISA with the compressed extension. Question 38. When cross‑compiling for a RISC‑V target on an x86 host, which option specifies the target triple?
Associate Practice Exam
A) --target=riscv64-unknown-elf B) --host=x86_64-linux-gnu C) --build=riscv64-linux-gnu D) --sysroot=/riscv/sysroot Answer: A Explanation: The --target option defines the target architecture, vendor, OS, and ABI. Question 39. In the RISC‑V ELF ABI, which registers are used to pass the first eight integer arguments to a function? A) a0‑a B) t0‑t C) s0‑s D) x0‑x Answer: A Explanation: a0‑a7 are the standard argument registers in the RISC‑V calling convention. Question 40. Which register typically holds the return address for a function call? A) sp B) ra C) s D) gp Answer: B Explanation: ra (x1) stores the address to return to after a jal or function call. Question 41. The stack pointer sp in RISC‑V is conventionally aligned to:
Associate Practice Exam
Question 44. The RISC‑V ecall instruction is used for: A) Raising an exception due to illegal instruction B) Performing a system call / environment call C) Exiting the processor core D) Enabling interrupts Answer: B Explanation: ecall triggers a synchronous trap to the environment, commonly used for system calls. Question 45. OpenSBI primarily provides which functionality for RISC‑V systems? A) A full Linux kernel B) Firmware that implements the supervisor‑binary‑interface (SBI) for booting OSes C) An instruction‑set simulator D) A JTAG debugger Answer: B Explanation: OpenSBI implements the SBI, allowing higher‑level software (e.g., Linux) to interact with the hardware. Question 46. In RISC‑V, the privilege level that most embedded RTOS kernels run in is: A) Machine mode (M) B) Supervisor mode (S) C) User mode (U) D) Hypervisor mode (H) Answer: B Explanation: RTOS kernels typically run in supervisor mode to manage resources while keeping user tasks in U‑mode.
Associate Practice Exam
Question 47. Which of the following is a valid page‑table entry field in the Sv39 scheme? A) V (valid) bit at bit 0 B) G (global) bit at bit 1 C) D (dirty) bit at bit 2 D) All of the above Answer: D Explanation: Sv39 PTEs contain V, G, D, A, and other bits as defined by the privileged spec. Question 48. The RISC‑V instruction fadd.s f1, f2, f3 performs: A) Integer addition of registers f2 and f3, result in f B) Single‑precision floating‑point addition of f2 and f3, result in f C) Double‑precision floating‑point addition D) Fixed‑point addition Answer: B Explanation: The .s suffix denotes single‑precision floating‑point operations. Question 49. Which tool provides cycle‑accurate functional simulation of a RISC‑V core? A) QEMU B) Spike C) GDB D) OpenOCD Answer: B Explanation: Spike (the RISC‑V ISA simulator) models the core at a functional level and can be configured for cycle accuracy.
Associate Practice Exam
Explanation: The MPP field in mstatus records the previous privilege level; the current level is implicit by the mode the core is executing in. Question 53. In the RISC‑V privileged spec, which CSR controls delegation of traps from machine to supervisor mode? A) medeleg B) mideleg C) mtvec D) mscratch Answer: A Explanation: medeleg contains bits that delegate exception handling to S‑mode. Question 54. The sstatus CSR is analogous to mstatus but is used in which mode? A) Machine mode only B) Supervisor mode C) User mode D) Hypervisor mode Answer: B Explanation: sstatus mirrors many of the fields of mstatus for S‑mode. Question 55. Which of the following is true about the t0‑t6 registers? A) They are callee‑saved registers. B) They are caller‑saved registers. C) They are used exclusively for floating‑point values. D) They are read‑only.
Associate Practice Exam
Answer: B Explanation: t0‑t6 are temporary registers that the caller must assume may be clobbered. Question 56. The s0‑s11 registers are also known as: A) Argument registers B) Saved registers (callee‑saved) C) Temporary registers D) Zero register Answer: B Explanation: s0‑s11 must be preserved across function calls by the callee. Question 57. Which pseudo‑instruction expands to addi rd, x0, imm when the immediate fits in 12 bits? A) li B) mv C) nop D) ret Answer: A Explanation: li loads an immediate using addi when it can be encoded directly. Question 58. The ret pseudo‑instruction is equivalent to which real instruction? A) jalr x0, 0(ra) B) jalr ra, 0(x1) C) jalr x0, 0(ra) D) jalr x0, 0(x1)
