Design and Implementation of Digital Logic Circuits using NAND Gates: Exercise E51IFE, Exams of Logic

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Version 1.0 (24 March 2016)

Laboratory of electronics

Exercise E51IFE

Design and implementation of digital logic circuits

using NAND gates

Table of contents:

• 1. Purpose of the exercise
• 2. Hazards
• 3. Introduction
  • 3.1. Basic logical functions and gates
  • 3.2. Minimization and synthesis of combinational logic circuits...........................................
• 4. Available equipment.............................................................................................................
  • 4.1. The block of logic state switches
  • 4.2. The table of logic gates
  • 4.3. The block of logic probes..............................................................................................
  • 4.4. Power supply
• 5. Experimental procedure......................................................................................................
  • 5.1. Verification of De Morgan’s law.................................................................................
  • 5.2. Design and implementation of combinational logic circuit.........................................
  • 5.3. Examples of problems to solve by combinational logic circuit...................................
• 6. Report elaboration
• 7. References
  • 7.1. Basic reference materials...............................................................................................
  • 7.2. Other reference materials

• conjunction, logical product, also known as AND operator: Y = A ⋅ B ,
• disjunction, logical sum, also known as OR operator: Y = A + B ,
• logical negation, NOT operator: Y = A. In practice, it is very useful to introduce the composition of NOT and AND operators, as well as the composition of NOT and OR operators:
• negation of the conjunction, NAND: Y = A ⋅ B ,
• negation of the disjunction, NOR: Y = A + B. The symbols of electric devices (called logic gates) which are performing the functions listed above are given in Fig. 1. The definitions of the AND, OR, NAND, and NOR operators can be easily extended to any number of arguments by employing the composition of two-argument operators, such as A · B · C = ( A · B )· C.

A B Y

A B Y

A B Y

A B Y

A Y

Fig. 1. The symbols of additional logic gates and their truth tables.

Moreover, two additional derived operators are very important in practice. The first is called exclusive-or (EX-OR) or parity (in Polish: operator ALBO, WYŁĄCZNE LUB). The second is defined as the negation NOT of EX-OR (EX-NOR) and is called logical biconditional, logical equality, or logical equivalence (in Polish: funkcja równoważności lub funkcja tożsamości).

• exclusive disjunction, EX-OR operator: Y = A ⊕ B = A ⋅ B + A ⋅ B ,
• logical biconditional, EX-NOR operator: Y = A ⊗ B = A ⋅ B + A ⋅ B.

A B Y

A B Y

Fig. 2. The symbols of additional logic gates and their truth tables.

To design the logic circuits the following laws of Boolean algebra are commonly used: commutativity, associativity, distributivity, and De Morgan's laws. Note that distributivity of disjunction over conjunction and both De Morgan’s laws do not have their counterparts in ordinary algebra of real numbers.

Property For conjunction For disjunction Commutativity A ⋅ B = B ⋅ A A + B = B + A Associativity A ⋅ ( B ⋅ C )=( A ⋅ B )⋅ C A + ( B + C )=( A + B )+ C Distributivity A ⋅ ( B + C )= A ⋅ B + A ⋅ C A + B ⋅ C =( A + B )⋅( A + C ) De Morgan's laws (^) A ⋅ B ⋅K = A + B +K A + B +K = A ⋅ B ⋅K Basic identities A ⋅ 0 = 0 A ⋅ 1 = A A ⋅ A = A A ⋅ A = 0

A + 1 = 1 A + 0 = A A + A = A A + A = 1 Additional identities A ⋅ (A + B) = A A + A ⋅ B = A + B ( A + B )⋅( A + B )= B

A + A ⋅ B = A A ⋅ (A + B) = A ⋅ B A ⋅ B + A ⋅ B = B

Table 1. Principal identities and laws of Boolean algebra.

Using De Morgan’s laws it can be proved that only NAND and NOR logic gates are universal. All other types of Boolean operators (i.e., AND, OR, NOT, EX-OR, and EX-NOR) can be implemented as a suitable network of just NAND or just NOR gates. Reduction of a set of logical functors used to implement any Boolean function has many advantages and is often used in practice.

3.2. Minimization and synthesis of combinational logic circuits

Suppose that analysis of a certain control problem led to the following truth table, which describes the response W of a system for all possible logic states of the four inputs A , B , C , and D.

A B C D W A B C D W 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 – 1 1 1 1 –

Table 2. A logical function written in the form of a truth table. Dash (–) are used for cases in which the logic state of output does not matter.

If one is given a truth table of a Boolean function, it is easy to write the function in a canonical sum form, i.e. as a sum of minterms, where each minterm is a logical product of all input variables in either literal or negated form and is related to one unique row, which has output W = 1 in the truth table

W = ( ACD )( ABD )( AC ), (5)

W = ( AC )( AD )( ABC ). (6)

Note, that all operations occurring in Eq. (5) can be implemented directly employing assumed available gates, while the outer logical product (AND) in Eq. (6) must be expressed as a negation (NOT) of negated product (NAND)

W = ( AC ) ( AD ) ( ABC ). (7)

As seen in figures 4 and 5 a hardware implementation of the function given by Eq. (7) requires more NOT gates than in the case of Eq. (5), but smaller number of inputs of NAND gates in the circuit shown in Fig. 5 leads to a similar amount of work effort when building both systems. These solutions, however, are not equivalent in terms of signal propagation time from inputs to output.

Fig. 4. Schematic of a system implementing the function (5).

Fig. 5. Schematic of a system implementing the function (7).

4. Available equipment

4.1. The block of logic state switches

The block of logic state switches are composed of five switches, which allow to select 0 or 1 logic state at the sockets below the switches. When more than five independent inputs must be driven, please use also the sockets on the bottom of the front panel, which has fixed 0 or 1 state. Moreover, the block contains three generators of single square pulse. The generators are used only to investigate sequential logic circuits, which go beyond the scope of the present experiment.

Fig. 6. The front panel of the block of logic state switches.

4.2. The table of logic gates

The table of logic gates contains 4 NOT gates, 8 two-input NAND gates, and 8 three-input NAND gates (fig. 7a). All other functors must be implemented as a network of available NAND and NOT gates. Alternatively, a set of 12 two-input NAND gates and 8 three-input NAND gates (Fig. 7b) may be available in the laboratory. The missing NOT gate may be implemented e.g. as two-input NAND gate with a jumper between the inputs.

4.3. The block of logic probes

The block of logic probes contains 10 independent channels (fig. 8). There are a one input socket for each channel with red and green LED lights, which indicate the high and low logic state, respectively. When the investigated state changes continuously the both lights may be visible. Oscillations should not appear in correct combinational circuits, so if it occurs, you should check the network of connections. When the input of logic probe is in the high-resistance state or the applied voltage does not correspond to any specific logic state, the both lights are switched off. If the input of logic probe is connected with the output of any logic gate or logic state switch, such a situation indicates a failure of the cable or device, or a lack of power supply.

Fig. 8. The front panel of the block of logic probes.

4.4. Power supply

All experimental modules described above are powered by a single laboratory power supply SIGLENT SPD3303D [10]. Among the three channels of this power supply only the channel with a fixed voltage of +5V DC is used in this exercise. Alternatively, plug-in power supply +5V DC with cable terminated with banana plugs may be available in the laboratory.

5. Experimental procedure

First, you need to prepare your own project of combinational logic circuit. Then, you can begin to connect the circuit according to the project using available logic gates. The response of your circuit will be investigated by logic probe for all combinations of input states. Next, the experimental truth table will be compared with the theoretical one.

5.1. Verification of De Morgan’s law

1. Use De Morgan’s law related to logical disjunction (see Table 1) to draw a diagram of the circuit that implements two-input OR gate using available NAND and NOT gates.
2. Construct the circuit, wire the inputs to the switches of logic state, and wire the output to the logic probe tester.
3. Connect the power supply to all experimental modules. In order to do this connect the extreme left or extreme right module directly to the power supply. The other modules will be supplied through the connections of analogous +5V lines (on the top) and 0V lines (at the bottom) between the neighboring modules. WARNING: a) all modules must be supplied from the power supply channel that provides constant output voltage +5 V (sockets on the right side of the power supply). Do not use the outputs allowing voltage adjustment, b) Do not connect +5V voltage output directly to the outputs of gates nor outputs in the block of logic state switches. Ignoring these recommendations threatens to damage the devices.
4. After obtaining permission switch on the power supply and check out the status of the red LEDs on the +5V line. The LEDs related to the 0 and 1 logic states should be off when the appropriate input of logic probe tester is not connected.
5. Set up all possible combinations of input logic states and write down the truth table for the circuit. Compare your experimental truth table with the theoretical one shown in Fig. 1. In the case of any discrepancies check out the circuit again. If you can not resolve the problem consult with the laboratory staff.

5.2. Design and implementation of combinational logic circuit

1. Consult the supervisor in order to select some tasks to solve. Some examples of tasks are collected in the next chapter.
2. Develop a theoretical truth table (see example show in Table 1). The cases when the state of output does not matter write as a dash.
3. Try to simplify your Boolean function using the Karnaugh map method. Consider a grouping of “1s” (see example shown in Fig. 3.a) as well as grouping of “0s” (Fig. 3.b).
4. Use the laws of Boolean algebra to transform simplified function. After transformation the function must be written employing only these elementary operators, which are directly implemented in available hardware (the table of NOT and two- and three-inputs NAND gates allow to use only A , A ⋅ B , and A ⋅ B ⋅ C operators). If more than one output is necessary in the circuit, find common expressions in the Boolean functions related to the individual outputs. Try to simplify the circuit by implementing the common expressions only ones.

7. (***) Design and implement the control system for a dryer equipped with two heaters G 1 and G 2 with a power 4 kW and 2 kW, respectively. The heaters can be connected in different ways by electromagnetic switches w 1 , w 2 , and w 3. The settings of switches shown in the diagram is related to the logical 0, while the position opposed consider as a logical 1. The temperature in a drying chamber is measured by an electric contact thermometer, which has four contacts A , B , C , D. When the temperature is increasing the contacts change its state from 0 to 1 in mentioned order. Let ti denote the temperature of switching of the i -th contact. Mode of action of the control system will be as follows: t < t A – both heaters are connected in parallel, t A ≤ t < t B – only the heater G 1 is switched on, t B ≤ t < t C – only the heater G 2 is switched on, t C ≤ t < t D – both heaters are connected in series, t D ≤ t – both heaters are switched off.
8. (***) Design and implement the driver controlling the line consisting of four LEDs, which are turned on sequentially. Number of currently shining LEDs is given by the four-bit binary value at the input of controller. When this value is greater than 0100 (4 in decimal code) all LEDs should be lit up.
9. (****) Design and implement a 1-bit full adder. The circuit performs an addition operation on three binary digits Ai , Bi , and carry-in Ci -1. The latter input allows to take into account the carry-out of the previous adder. The adder produces a sum Si and carry-out signal Ci for the next adder operating on more significant bits.

6. Report elaboration

Report has to be composed of:

1. Front page (by using a pattern).
2. Description of experiment purpose.
3. List of used instruments and devices (id number and type). In the case of the table of logic gates provide full specification of available gates (types of gates, number of inputs, number of available gates).
4. Description of De Morgan’s law verification.
5. Description of the problem, which should be solved by your combinational circuit.
6. Theoretical truth table for each output.
7. Minimization of logical function, e.g. using Karnaugh map method or laws of Boolean algebra.
8. Transformation of obtained minimized functions to the form, which may be directly implemented using available gates.
9. Schematic diagrams of designed combinational circuits.
10. Experimental truth table.
11. Discussion and conclusions. Compare the results obtained with your theoretical assumptions. In the case of any discrepancy, describe your attempts to remove them, found errors and finally obtained result. Have you found the Karnaugh map method helpful for finding non-trivial simplification of your circuit?

w 1

G 1 4 kW

w 2

G 2 2 kW

w 3

Circuit diagram for the

The report will be evaluated for the language, completeness, correctness, clarity of presentation of the results (in the form of tables, functions and circuit diagrams together with descriptions) and quality of discussion and conclusions. All of the components listed above will be evaluated in the report. Theoretical introduction is not required and is not included in the assessment. Moreover, the assessment for the complete and correct report depend on the total number of marks received for the solutions documented in the scratchpad and approved by the supervisor. Unless the supervisor has specified otherwise, the following table applies:

The sum of marks for solved problems The highest score of the report on a scale of 0 ... 5 points 0 failed 1 2 pkt. 2 3 pkt. 3 4 pkt. ≥ 4 5 pkt.

7. References

7.1. Basic reference materials

[1] J. Kalisz, Podstawy elektroniki cyfrowej , WKiŁ, Warszawa 2002. [2] P. Horowitz, W. Hill, Sztuka elektroniki , WKiŁ, Warszawa 2001, [3] U. Tietze, Ch. Schenk, Układy półprzewodnikowe , WNT, Warszawa 2009. [4] M. Molski, Wstęp do techniki cyfrowej , WKiŁ, Warszawa 1989. [5] R. Ćwirko, M. Rusek, W. Marciniak, Układy scalone w pytaniach i odpowiedziach , WNT, Warszawa, 1987. [6] W. Traczyk, Układy cyfrowe. Podstawy teoretyczne i metody syntezy , WNT, Warszawa

[7] P. Misiurewicz, Układy automatyki cyfrowej, Wydawnictwa Szkolne i Pedagogiczne, Warszawa, 1984. [8] A. Rusek, Podstawy elektroniki , część 2, Wydawnictwa Szkolne i Pedagogiczne, Warszawa, 1983. [9] W. Głocki, Układy cyfrowe , Wydawnictwa Szkolne i Pedagogiczne, Warszawa, 2008.

7.2. Other reference materials

[10] B. Zbierzchowski, T. Łuba, K. Jasiński, M. A. Markowski, Synteza logiczna w układach programowalnych , Wydawnictwa Politechniki Warszawskiej, Warszawa, 1992.