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An overview of fault models, common faults, and their equivalence and dominance in vlsi and printed circuit boards (pcb). It covers single stuck-at faults, transistor faults, memory faults, pla faults, delay faults, and multiple stuck-at faults. The document also discusses the effectiveness of fault modeling and the use of simulation for verification and design purposes.
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EECS 579: Digital Testing
Why model faults?
Some real defects in VLSI and PCB
Common fault models
Stuck-at faults
Single stuck-at faults
Fault equivalence
Fault dominance and checkpoint theorem
Classes of stuck-at faults and multiple faults
Transistor faults
Summary
EECS 579: Digital Testing
I/O function tests inadequate forI/O function tests inadequate forI/O function tests inadequate forI/O function tests inadequate formanufacturing (functionality versusmanufacturing (functionality versusmanufacturing (functionality versusmanufacturing (functionality versuscomponent and interconnect testing)component and interconnect testing)component and interconnect testing)component and interconnect testing)
Real defects (often mechanical) tooReal defects (often mechanical) tooReal defects (often mechanical) tooReal defects (often mechanical) toonumerous and often not analyzablenumerous and often not analyzablenumerous and often not analyzablenumerous and often not analyzable
A fault model identifies targets for testingA fault model identifies targets for testingA fault model identifies targets for testingA fault model identifies targets for testing
A fault model makes analysis possibleA fault model makes analysis possibleA fault model makes analysis possibleA fault model makes analysis possible
Effectiveness measurable by experimentsEffectiveness measurable by experimentsEffectiveness measurable by experimentsEffectiveness measurable by experiments
EECS 579: Digital Testing
Defect classesShortsOpensMissing componentsWrong componentsReversed componentsBent leadsAnalog specificationsDigital logicPerformance (timing)
Occurrence frequency (%)
Ref.: J. Bateson,
In-Circuit Testing
, Van Nostrand Reinhold, 1985.
EECS 579: Digital Testing
Single stuckSingle stuckSingle stuckSingle stuck-
at faultsat faultsat faults
Transistor open and short faultsTransistor open and short faultsTransistor open and short faultsTransistor open and short faults
Memory faultsMemory faultsMemory faultsMemory faults
PLA faults (stuckPLA faults (stuck-PLA faults (stuckPLA faults (stuck
-at, cross--
at, cross-at, crossat, cross
-point, bridging)--
point, bridging)point, bridging)point, bridging)
Functional faults (processors)Functional faults (processors)Functional faults (processors)Functional faults (processors)
Delay faults (transition, path)Delay faults (transition, path)Delay faults (transition, path)Delay faults (transition, path)
Analog faultsAnalog faultsAnalog faultsAnalog faults
For more examples, see Section 4.4 (p. 60For more examples, see Section 4.4 (p. 60-For more examples, see Section 4.4 (p. 60For more examples, see Section 4.4 (p. 60
F 2002
EECS 579: Digital Testing
Number of fault sites in a Boolean gate circuit= #PI + #gates + # (fanout branches).
Fault equivalence: Two faults f1 and f2 areequivalent if all tests that detect f1 alsodetect f2.
If faults f1 and f2 are equivalent then thecorresponding faulty functions are identical.
Fault collapsing: All single faults of a logiccircuit can be divided into disjoint equivalencesubsets, where all faults in a subset aremutually equivalent.
A collapsed fault set
contains one fault from each equivalencesubset.
F 2002
EECS 579: Digital Testing
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa
sa0sa
sa
sa
sa
sa
sa
sa
sa
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ANDANDANDAND
NANDNANDNANDNAND
OROROROR
NORNORNORNOR
WIREWIREWIREWIRE
NOTNOTNOTNOT
FANOUT FANOUT
FANOUT FANOUT
F 2002
EECS 579: Digital Testing
If all tests of some fault F1 detect another faultF2, then F2 is said to dominate F1.
Dominance fault collapsing: If fault F2dominates F1, then F2 is removed from thefault list.
When dominance fault collapsing is used, it issufficient to consider only the input faults ofBoolean gates.
See the next example.
In a tree circuit (without fanouts) PI faults forma dominance collapsed fault set.
If two faults dominate each other then they areequivalent.
EECS 579: Digital Testing
s-a-
F
s-a-
F
001
110
010
000
101
100
011
All tests of F
Only test of F
s-a-
s-a-
s-a-
s-a-
A dominance collapsed fault set
F 2002
EECS 579: Digital Testing
Following classes of single stuck-at faults areidentified by fault simulators:
Potentially-detectable fault
-- Test produces an
unknown (X) state at
primary output
(PO);
detection is
probabilistic, usually with 50%
probability.
Initialization fault
-- Fault prevents initialization of
the faulty circuit; can be detected as a potentially-detectable fault.
Hyperactive fault
-- Fault induces much internal
signal activity without reaching PO.
Redundant fault
-- No test exists for the fault.
Untestable fault
-- Test generator is unable to find
a test.
EECS 579: Digital Testing
A multiple stuck-at fault means that any setof lines is stuck-at some combination of (0,1)values.
The total number of single and multiplestuck-at faults in a circuit with
k
single fault
sites is 3
k
A single fault test can fail to detect thetarget fault if another fault is also present,however, such masking of one fault byanother is rare.
Statistically, single fault tests cover a verylarge number of multiple faults.
EECS 579: Digital Testing
Two-vector s-op testcan be constructed byordering two s-at tests
DDDDDDDD
pMOS
FETs
nMOS
FETs
Stuck-
open
1 0
0 0
0
1(Z)
Good circuit states
Faulty circuit states
Vector 1: test for
A
s-a-
(Initialization vector)Vector 2 (test for
A
s-a-1)
EECS 579: Digital Testing
DDDDDDDD
pMOS
FETs
nMOS
FETs
Stuck-
short
1 0
0 (X)
Good circuit state
Faulty circuit state
Test vector for
A
s-a-
I
DDQ
path in
faulty circuit
EECS 579: Digital Testing
What is simulation?
Design verification
Circuit modeling
True-value simulation algorithms
Compiled-code simulation
Event-driven simulation
Summary
EECS 579: Digital Testing
Definition: Simulation refers to modeling of adesign, its function and performance.
A software simulator is a computer program;an emulator is a hardware simulator.
Simulation is used for design verification:
Validate assumptions
Verify logic
Verify performance (timing)
Types of simulation:
Logic or switch level
Timing
Circuit
Fault
