Finite State Machine Design: Minimizing States and State Reduction - Prof. Travis Doom, Study notes of Digital Systems Design

The finite state machine design process, focusing on minimizing the number of states and state reduction techniques. It includes examples and explanations using a four-bit sequence detector. The advantages of minimizing states and algorithms for state reduction are also covered.

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Uploaded on 08/18/2009

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Finite State Machine Design
The Finite state machine design process consists of
1. Constructing an initial state machine that realizes the design.
2. Minimizing the number of states.
3. Encoding the states.
4. Choosing the memory device to implement the state memory.
5. Implementing the finite state machine’s next state and output functions.
In the age of very large scale integrated circuits, why should we bother to
minimize a state machine implementation? After all as long as the input/output behavior
of the machine is correct, it doesn’t matter how it is implemented. Or does it?
Advantages of minimum states
In general, you will find it is worthwhile to implement the finite state machine in as
few states as possible. This usually reduces the number of gates and flip-flops you need
for the machine implementation. For example, you are given a finite state machine with 18
states, thus requiring five state flip-flops. If you can reduce the number of states to 16 or
less, you save a flip-flop. Even if reducing the reducing the number of states is not enough
to eliminate a flip-flop, it still has advantages. With fewer states, you introduce more don’t
care conditions into the next-state and output functions, making their implementation
simpler. State reduction technique also allows you to be less meticulous in obtaining the
initial finite state machine description. If you have introduced a few redundant states, you
will find and eliminate them by using the state reduction technique introduced next.
State Minimization
State reduction identifies and combines states that have equivalent behavior. Two
states have equivalent behavior if, for all the input combinations, their outputs are the
same and they change to the same or equivalent next states. Algorithms for state reduction
begin with the symbolic state transition table. First we group together states that have
same state outputs (Moore machine) or transition outputs (mealy machine). These are
potentially equivalent, since states cannot be equivalent if their outputs differ. Next, we
examine the transitions to see if they go to the same next state for every input
combination. If they do, the states are equivalent and we can combine them into a renamed
new state. We then update all transitions to the newly combine states. We repeat this
process until no additional states can be combined.
There are two common methods by which states can be minimized.
1. Row-matching method.
2. Chart method.
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Finite State Machine Design

The Finite state machine design process consists of

  1. Constructing an initial state machine that realizes the design.
  2. Minimizing the number of states.
  3. Encoding the states.
  4. Choosing the memory device to implement the state memory.
  5. Implementing the finite state machine’s next state and output functions. In the age of very large scale integrated circuits, why should we bother to minimize a state machine implementation? After all as long as the input/output behavior of the machine is correct, it doesn’t matter how it is implemented. Or does it?

Advantages of minimum states

In general, you will find it is worthwhile to implement the finite state machine in as few states as possible. This usually reduces the number of gates and flip-flops you need for the machine implementation. For example, you are given a finite state machine with 18 states, thus requiring five state flip-flops. If you can reduce the number of states to 16 or less, you save a flip-flop. Even if reducing the reducing the number of states is not enough to eliminate a flip-flop, it still has advantages. With fewer states, you introduce more don’t care conditions into the next-state and output functions, making their implementation simpler. State reduction technique also allows you to be less meticulous in obtaining the initial finite state machine description. If you have introduced a few redundant states, you will find and eliminate them by using the state reduction technique introduced next.

State Minimization

State reduction identifies and combines states that have equivalent behavior. Two states have equivalent behavior if, for all the input combinations, their outputs are the same and they change to the same or equivalent next states. Algorithms for state reduction begin with the symbolic state transition table. First we group together states that have same state outputs (Moore machine) or transition outputs (mealy machine). These are potentially equivalent, since states cannot be equivalent if their outputs differ. Next, we examine the transitions to see if they go to the same next state for every input combination. If they do, the states are equivalent and we can combine them into a renamed new state. We then update all transitions to the newly combine states. We repeat this process until no additional states can be combined. There are two common methods by which states can be minimized.

  1. Row-matching method.
  2. Chart method.

Row Matching Method

Let’s begin our investigation of a row-matching method with detailed example. We will see how to transform an initial state diagram for a simple sequence detector into a minimized, equivalent state diagram. Four-Bit Sequence Detector: Specification and Initial state diagram. Let’s consider a sequence-detecting finite state machine with following specifications. The machine has single input X and output Z. The output is asserted after each four bit input sequence if it consists of one of the binary strings 0110 or 1010. The machine returns to the reset state after each four-bit sequence will assume mealy implementation. The state diagram of 4-bit sequence detector is as shown below: Reset 0/0 1/ 0/0 1/0 0/0 1/ 0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/ 0/0 1/0 0/0 1/0 0/0 1/0 0/1 1/0 0/0 1/0 0/1 1/0 0/0 1/ 0/0 1/ There are 16 unique paths through the state diagram, one for each possible 4-bit pattern. This requires 15 states and 30 transitions. Only two of the transitions have a one output, representing the accepted strings.

We continue matching rows until we can no longer combine any. In the above figure S7, S8, S9 S11, S13, and S14 all have the same next state and the outputs. We combine them into a renamed state S7`. The table with renamed transitions, is shown in the figure below. Input Sequence Present State Next State X=0 X= Output X=0 X= Reset S0 S1 S2 0 0 0 1

S

S

S3 S

S5 S

S

S

S

S

S7S7

S7S10

S7S10

S7S7

Not(011 or 101) 011 or 101

S7`

S10`

S0 S

S0 S

Now state S3 and S6 can be combined, as can S4 and S5. We call the combined states S3and S4 respectively. The final reduced state transition table is as shown below. Input Sequence Present State Next State X=0 X= Output X=0 X= Reset S0 S1 S2 0 0 0 1

S

S

S3S4

S4S3

00 or 11 01 or 10

S3`

S4`

S7S7

S7S10

Not(011 or 101) 011 or 101

S7`

S10`

S0 S

S0 S

In the process we have reduced 15 states to just 7 states. The reduced state diagram is as shown below. Reset 0/0 1/ 1/0 1/ 0/0 0/ 0,1/0 0/0 1/ 0,1/0 0/1 1/

Chart Method : The implication Chart method is a more systematic approach to finding the states that can be combined into a single reduced state. Consider a Three -Bit Sequence Detector: Your goal is to design a binary sequence detector that will output a 1 whenever a machine has observed the serial sequence 010 or 110 at the inputs. The initial table is as shown below. Input Sequence Present State Next state X=0 X= Output X=0 X= Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 The method operates on a data structure that enumerates all possible combinations of states taken two at a time, called an implication chart. S S S S S S S S0 S1 S2 S3 S4 S5 S The chart shown above is more complicated then it needs to be. For example the diagonal entries are not needed since we do not need to compare a state with itself. Also note that al the upper and the lower triangles of cells are symmetric. The chart cell for row Si and column Sj considers the same information as that for row Sj and column Si. Therefore, we work with the following reduced structure.

Initial Entries:

  • S1-S
  • S2-S
  • S1-S5 S3-S
  • S2-S4 S4-S
  • S1-S0 S3-S0 S5-S
  • S2-S0 S4-S0 S6-S
  • S1-S0 S3-S0 S5-S0 S0-S
  • S2-S0 S4-S0 S6-S0 S0-S - S0-S - S0-S
    • S0 S1 S2 S3 S4 S
  • S First Pass:
  • S2 S3-S - S4-S
  • S
  • S
  • S5 S0-S - S0-S
  • S6 S0-S - S0-S - S0 S1 S2 S3 S4 S

The above figure contains the results of first making pass. Entry S2-S0 is marked with X because the chart entry for the implied state pair S2-S6 is already marked with a X. Entry S3-S0 is also marked, because S1-S0 has just been marked. The same is true for S5-S0.by the end of the pass; the only entries not marked are S2-S1, S5-S3 and S6-S4. We now make a second pass through the chart to see if we can add any new markings. Entry S2-S1 remains unmarked. Nothing in the chart refuses that S3 and S5 are equivalent. The same is true of S4 and S6. Continuing S3-S5 and S4-S6 are now obviously equivalent. They have identical outputs and transfer to the same next state (S0) for all input combinations. Since no marking have been added the algorithm stops. The unmarked entries represent equivalence between the row and the column indices. The final reduced state table is as shown. Input sequence Present State Next State X=0 X= Output X=0 X= Reset S0 S1S1 0 0 0 or 1 00 or 10 01 or 11

S1`

S3`

S4`

S3S4

S0 S

S0 S

Reference Books:

 Contemporary Logic Design by Randy H. Katz  Principles of Digital Design by Daniel H. Gajski  Digital Logic and State Machine Design by David J. Comer  Modern Digital Electronics by R.P.Jain