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• Flip-flops
• Combining flip-flops with combinatorial
logic
• Counter design
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Understanding NAND Latch and J-K Flip-Flops in Digital Electronics - Prof. Andrew Fagg, Assignments of Aerospace Engineering
An in-depth explanation of nand latch and j-k flip-flops in digital electronics. It covers the functionality, initial and stable states, and timing diagram representation of nand latch. Additionally, it discusses the operation of j-k flip-flops and their differences from nand latch. Essential for students studying digital electronics, microcontrollers, and computer organization.
Typology: Assignments
Pre 2010
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Last Time
- Flip-flops• Combining flip-flops with combinatoriallogic• Counter design
Today
- A bit more on flip-flops• Memory• Microcontroller essentials
NAND LatchWhat does this circuit do?
NAND LatchConsider this initial state 1 Is this a stable state?
1 Yes!
NAND LatchWhat happens with S is set to 0? 0 Q becomes 1 (thus S ‘sets’ Q)
NAND LatchNow S is set 1 – what happens? 1
NAND LatchNow set R to 0 – what happens? 1
NAND LatchNow set R to 0 – what happens? 1 The state flips back (Q is ‘reset’)
NAND LatchFinally: set R to 1 – what happens? 1 Q and Q’ do not change state
Timing Diagram Representation S R Q^? Q’
Timing Diagram Representation S R Q Q’
When S returns to high –both Q and Q’ remain inthe same state
Timing Diagram Representation S R Q Q’
?
Timing Diagram Representation S R Q Q’
How about this case?
Timing Diagram Representation S R Q Q’
No change in Q and Q’