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EECS 40 Midterm
Fall 2001 Professor Oldham Guidelines:
- Closed book and notes except 1 page of formulas.
- You may use a calculator
- Do not unstaple the midterm.
- Show all your work and reasoning on the exam in order to receive full or partial credit.
- This exam contains 6 problems and corresponding worksheets plus the cover page.
- Do not ask questions during the exam. If you believe there is an error, please point it out. If you believe there is anambiguity, explain your interpretation in your answer.
Problem 1 (15 points) Hint: Use the easiest possible method to solve these problems. (a) In the circuit below, find VA, V B, V C.
(b) In the circuit below, find VA, V B, V C.
(c) Calculate a sufficient number of points to draw the I versus V characteristics of the following circuit. Draw the graphon the axes provided. Be sure the label the axes.
(a) What are the values of VA, VB , VC, VD, iB at t = 0-? (b) What are the values of V A, V B, VC, VD, iB at t = 0+? (c) What are the values of VA, VB , VC, VD, iB at t >> 0? (d) On the axes, please make a neat sketch of VC(t). Label the axes.
(e) Write an equation for VC(t). Problem 3 (17 points) A three-digit binary number ABC has "even parity" if an even number of its digits is 1 or none of its digits is 1. Wedefine a logic variable E that is 1 if ABC has even parity.
(a) Write a truth table for E, that is, the combinations of ABC having even parity.
(b) Write a Boolean expression in sum-of-products form for E. (c) Draw a logic circuit for E, constructed only of inverters, OR gates, and AND gates. (d) Draw a logic circuit for E, constructed only of NAND gates and inverters. Problem 4 (16 points) - Nodal Analysis
Problem 5 (16 points) A recent Stanford graduate has designed an improvement to a BART controller logic circuit. The logic diagram is below.It has two inputs, A and B, and an output F. In this circuit the inverters, the NAND, and the AND gates all have a unit delay of 1 nsec.
(a) Given the input waveforms for A and B versus time shown, make a neat sketch of the logic response versus time forthe nodes X, Y, and F. (Assume that the values of A and B given at t = 0 were the same for a long time before 0.) Important: Make your timing sketch on the area provided below. Do this independently of part b. Hint: For your own use,you may want to sketch the invert of A on top of the graph for A.
(b) Being a smart Cal student, you think it is wise to check out the work of the high-paid Stanford engineer. Can youwrite down the logic expression for Y and for F? To get full credit you must derive and simplify the logic expression and you must show all of your work. Problem 6 (15 points) (a) You find a tremendous bargain on a transmogrifier at a flea market. You do not know what it is, but it's a great bigblack plastic box with two terminals and it's labeled "type 1 transmogrifier," and most importantly, the price is 50 cents. You take it home and measure its I-V characteristics and plot I versus V, as shown. Now your lab partner connects thedevice into the circuit shown and you find the box gets warm. How much power is the transmogrifier consuming when connected this way?
(b.1) Suppose Charlie has a response at a voltage of Vpulse under such conditions? SS = 1KV. How much energy are your delivering to him in one
(b.2) What is the efficiency of your energy delivering process, in other words, what fraction of the energy taken from Vis delivered to Charlie? SS
(b.3) How long should you keep the switch to the left to be sure that you have charged the capacitor to exactly 99% of thevalue of VSS? (Assuming the capacitor is initially uncharged.)
