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April 1, 2004 Page 1 of 4
Problem 1. (25 points)
A. (10 points) Each row in the table below lists a decimal value and its binary representation in both 6-bit sign-magnitude and 6-bit 2’s-complement formats. Complete the table, filling in the missing entries in each row.
Value (decimal)
6-bit sign-magnitude binary representation
6-bit 2’s-complement binary representation
27 0 1 1 0 1 1 0 1 1 0 1 1
- 19 1 1 0 0 1 1 1 0 1 1 0 1
22 0 1 0 1 1 0 0 1 0 1 1 0
- 11 **1 0 1 0 1 1 1 1 0 1 0 1
- 19 1 1 0 0 1 1** 1 0 1 1 0 1
B. (9 points) Perform each of the following additions using 6-bit 2’s-complement integer arithmetic. Write your answers in the boxes provided for each problem and circle the answers indicating the value of the carry-out bit and whether or not overflow occurred.
carry-out: 0 1 carry-out: 0 1 carry-out: 0 1
overflow: yes no overflow: yes no overflow: yes no
C. (6 points) Perform the following subtraction using 6-bit 2’s-complement integer arithmetic. Write your answer in the box provided and circle the answer indicating whether or not overflow occurred.
overflow: yes no overflow: yes no
April 1, 2004 Page 2 of 4
Problem 2. (18 points)
A. (6 points) A function is defined by the truth table given below. Draw the schematic for a circuit implement this function using either a 4-to-1 multiplexer or a 3-to-8 decoder as the key component, along with additional logic gates as needed.
A B C F
0 1 2 A 3 B 4 C 5 6 7
0 1 2 3
C 0 1 F (^) A B C
F
A B
B. Two clocked D latches and a multiplexer are to be used to implement a loadable D register that uses two-phase clocking.
(4 points) Draw a schematic for this memory element.
LOAD Φ 1 Φ 2
0 1
D Q D Q OUT
IN
(8 points) Complete the following timing diagram for this memory element, showing the value at the memory element output (OUT) and the point between the two laches (MID).
Phi 1 Phi 2 LOAD IN
MID
OUT
April 1, 2004 Page 4 of 4
Problem 4. (22 points)
A. (14 points) Each row in the following table describes a different memory system configuration. Fill in all of the missing entries. (NOTE: K=2^10 , M=2^20 , G=2^30 )
Total Memory Size
Total bits in memory
of memory
addresses
of
system address lines
of
system data lines
Size of individual memory ICs
Number of memory ICs needed
8G x 32 (^) 238 233 33 32 1G x 1 (^) 256
16M x 16 228 224^24 16 1M x 4^ 64
2M x 4 223^2 21 21^4 512K x 1^ 16
1G x 8^2 33 230^30 8 64M x 8^ 16
B. (8 points) Complete the schematic below for the implementation of a 4G x 8 memory system using four 2G x 4 memory chips. Clearly label the address bus, data bus, and control signals. Fill in the blanks below with the size of the address and data buses.
__ 32 ___ Number of bits in system address bus __ 8 ___ Number of bits in system data bus
1
4
8 4
32 31
MEM_EN
R/W
A … A
D … D
0 1
A 0 D 0
A 30 D 3
R/W CE
A 0 D 0
A 30 D 3
R/W CE
A 0 D 0
A 30 D 3
R/W CE
A 0 D 0
A 30 D 3
R/W CE
