ECE 6720 FUZZY CONTROL SYSTEMS
Fall 2008
Project Assignment #1
(Team Project)
Total: 120 pts. (30% of the course grade)
Due 6:30pm, Tuesday, November 11, 2008
Design, simulate and implement a segment of a fuzzy logic hardware accelerator module
(FLHA) for a single-input single-output model using VHDL along with Xilinx WebPack 10.1i
and Mentor Graphics ModelSim MXE-III tools. The accelerator should support both fuzzy model
building and inference computations. It is assumed that a host computer sends down fuzzified
input data in the form of long binary words to the accelerator through a 32-bit data bus, and it will
take the fuzzy output data (without defuzzification) generated by the FLHA in the case of an
inference operation. The simplified host processor interface has the signals as follows: D0 - D31
(Bidirectional Data Bus), RD* (Read - Active Low), WR* (Write - Active Low), RDY* (Ready -
Active Low), A2 - A0 (Address), SEL* (Select - Active Low) and RESET* (Active Low, same
effect than that of the CLEAR command below). You may assume that the signal SEL* (the output
of an address decoder circuit) is made available for you. When SEL* is at low level the host
processor is accessing to the register model of the FLHA module.
In order to facilitate pipelined operations, both the input and the output data of the FLHA should
be registered. The register model with respect to accessing to the resources of the FLHA by the
host machine is given below. When the accelerator is ready to transfer data between the selected
register and the data bus, it will assert signal RDY*. For the sake of simplicity, you may assume
that no delays (wait states) will be needed to access to the FLHA registers by the host machine.
Fuzzy input and output are denoted as X, and Z, respectively. The discrete representation of the
fuzzy data is as follows: there are 8 elements in each universal space, and the degree of
membership is a discrete set of 16 numbers in [0, 1]. Mathematical models to build a linguistic
model and to do inference for a SISO system are given in the Instructor's Lecture Notes. In
addition, parallel algorithms for model building and inference, respectively, are also given in the
Lecture Notes. You should include in your design a high-speed 8x32-bit Rule Memory Module
in the form of eight, individually accessible 32-bit registers to store the aggregated rule base
during model building and inference operations, respectively. Map your hardware accelerator to a
Xilinx Vertex-2 Pro XC2VP30-5FF896 FPGA chip (speed grade: -5, I/O attribute: PCI-X
compatible) when you create your project using the WebPack 10.1i tools.
Tasks:
a) Give a narrative summary along with a detailed schematic diagram of your circuit.
It should include host interface data, and control signals, a model/inference engine, and a
control unit. In the schematics, represent the Vertex-2 chip by a rectangular block with signal
names assigned to the appropriate pins. Also give the detailed design steps (i.e., a
functional block diagram, Truth Tables, and a state transition graph for the Control
Unit) along with your comments. For the sake of simplicity, low-voltage signal buffers for
the host interface are not required at this point. (24pts.)
b) Design, simulate and also run the implement step for the circuits mapped to your
Vertex-2 chip. Contents of the Rule Memory should be included in your simulations. Attach
