ASIC design and FPGA Lab
Lab 1
Introduction
Gate-level modeling
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Gate-level modeling-Verilog HDL-Lab Assignment, Exercises of Verilog and VHDL
Manish Saurin assigned this task in lab of Verilog HDL course at Birla Institute of Technology and Science. It includes: ASIC, Design, FPGA, Lab, Gate, Level, Modeling, Application, Specific, Integrated, Circuit, Fabrication, Cost
Typology: Exercises
2011/2012
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ASIC design and FPGA Lab
Lab 1
Introduction
Gate-level modeling
ASICs
•^
Application Specific Integrated Circuit (ASICs)
-^
ASIC is a dedicated piece of hardware designed for aparticular application. ASICs can be optimized for lowpower, low cost and high performance
e.g. Graphics
Chips,
dedicated
Cell
phone
designs
Chips,
dedicated
Cell
phone
designs
•^
ASICs are non flexible dedicated designs to enhanceperformance and speed
-^
Engineering and fabrication cost of an ASIC design canrun into millions of dollars, hence is preferred for largeproduction volumes
ASICs are everywhere
ASIC Design Flow
Verilog HDL
-^
Verilog originated at Gateway Design Automation in 1983- 1984
-^
Verilog enables modeling simulation and verification ofDigital systems at multiple level of abstraction
-^
Verilog based synthesis tools were developed by Synopsis in
-^
Verilog based synthesis tools were developed by Synopsis in 1987 which could convert a software code into gate-levelcircuit schematics
-^
Verilog was standardized in 1995 (OVI IEEE 1364)
-^
A common approach is to design any ASIC using HDL(Verilog) and verify system functionality via simulation
-^
Why Verilog HDL?
Verilog vs. VHDL
•^
Verilog HDL^
Verilog is easy to learn and close to C styleprogramming (syntax)
Verilog supports different levels of abstraction
Verilog has 60% of digital design market
Verilog has 60% of digital design market
•^
VHDL^
VHDL is ADA style language
VHDL is rigid and difficult to learn
Bottom-up Design Methodology
Levels of Abstraction in Verilog
-^
Verilog has multiple levels of abstraction
- Switch Level Design– Lowest level of abstraction provided by Verilog. Design at
this level is implemented in terms of switches andtransistors and interconnections between them.
- Gate Level Design• Gate Level Design – Design at this level is implemented in terms of logic gates
and interconnections between gates. All designoptimizations and logic minimization has to be done bydesigner
- Data Flow Design– Design at this level is specified in terms of data flow
between input and output connections and how thisdata is processed in between
Logic Synthesis
-^
Logic synthesis converts an HDL (Verilog) description of adesign into gate level netlist (description of circuit in terms ofgates and connections between them)
HDL Simulation & Synthesis Tools
Combinational Circuits
Sequential Circuits
•^
Sequential Circuits can be regarded as combinationalcircuits with feedback & memory elements
-^
A sequential circuit is specified by a time sequence ofinputs, outputs, and internal states
-^
Output of a sequential circuit depends upon the inputs
-^
Output of a sequential circuit depends upon the inputs and present state of the memory elements
-^
Sequential circuits can be divided into two categories
-^
- Asynchronous Sequential Circuit -^
- Synchronous Sequential Circuit