Homework 1 with Resolution | Systems Software | COP 3402, Assignments of Computer Science

Material Type: Assignment; Class: Systems Software; Subject: Computer Programming; University: University of Central Florida; Term: Fall 2007;

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University of Central Florida
School of Electrical Engineering & Computer Science
COP 3402: System Software
Fall 2007
Homework #1 (P-Machine)
Due Sept 17, 2007 by 11:59 p.m.
The P-machine:
In this assignment you have to implement an interpreter for a virtual machine known as the
P-machine (PM/0). The interpreter must describe a stack machine, consisting of a store
named โ€œstackโ€ organized as a stack and a โ€œcodeโ€ store that contains the instructions. The
CPU has four registers: register โ€œbpโ€ points to the base of the current activation record in
the stack, register โ€œspโ€ points to the top of the stack, a program counter (pc) and an
instruction register (ir).
The ISA of the PM/0 has 22 instructions and the instruction format has three components
<OP, L, M>:
OP is the operation code.
Lindicates the lexicographical level.
Mdepending of the operators it indicates:
- A number (instructions: LIT, INT).
- A program address (instructions: JMP, JPC, CAL).
- A data address (instructions: LOD, STO)
- The identity of the operator OPR(i.e. OPR 0, 2 (ADD) or OPR 0, 4 (MUL)).
The machine has two cycles known as fetch and execute.
Fetch cycle:
In the fetch cycle an instruction is fetch from the code store (ir ๏ƒŸ code[pc]) and the
program counter is incremented by one (pc ๏ƒŸ pc + 1).
Execute cycle:
In this cycle ir.op indicates the operation to be executed. In case ir.op = OPR then the field
ir.m is used to identified the operator and execute the appropriate arithmetic or logical
instruction.
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University of Central Florida

School of Electrical Engineering & Computer Science

COP 3402: System Software

Fall 2007

Homework #1 (P-Machine) Due Sept 17, 2007 by 11:59 p.m. The P-machine: In this assignment you have to implement an interpreter for a virtual machine known as the P-machine (PM/0). The interpreter must describe a stack machine, consisting of a store named โ€œstackโ€ organized as a stack and a โ€œcodeโ€ store that contains the instructions. The CPU has four registers: register โ€œbpโ€ points to the base of the current activation record in the stack, register โ€œspโ€ points to the top of the stack, a program counter (pc) and an instruction register (ir). The ISA of the PM/0 has 22 instructions and the instruction format has three components <OP, L, M>: OP is the operation code. L indicates the lexicographical level. M depending of the operators it indicates:

  • A number (instructions: LIT, INT).
  • A program address (instructions: JMP, JPC, CAL).
  • A data address (instructions: LOD, STO)
  • The identity of the operator OPR(i.e. OPR 0, 2 (ADD) or OPR 0, 4 (MUL)). The machine has two cycles known as fetch and execute. Fetch cycle: In the fetch cycle an instruction is fetch from the code store (ir ๏ƒŸ code[pc]) and the program counter is incremented by one (pc ๏ƒŸ pc + 1). Execute cycle: In this cycle ir.op indicates the operation to be executed. In case ir.op = OPR then the field ir.m is used to identified the operator and execute the appropriate arithmetic or logical instruction.

Instruction Set Architecture (ISA) : There are 13 arithmetic and decision instructions that work on implicit operands at the top of the stack. These instructions use the operator OPR to indicate that the instruction is an arithmetic or decision operation, and the modifier M to select the instruction to be executed. For example, to multiply the two elements on top of the stack we can write OPR 0,4. ISA: 01 - LIT 0, M Push constant value (literal) M onto stack 02 โ€“ OPR ( to be defined later) 03 โ€“ LOD L, M Push from location at offset M from frame L levels up. 04 โ€“ STO L, M Store in location at offset M from frame L levels up. 05 โ€“ CAL L, M Call procedure at M (generates new block mark and pc ๏ƒŸ M ). 06 โ€“ INC 0, M Allocate M locals (increment sp by M), first three are SL , DL , RA. 07 โ€“ JMP 0, M pc๏ƒŸ M ; 08 โ€“ JPC 0, M Jump to M if top of stack element is 0 and decrement sp by one. 09 โ€“ WRT 0, 0 ( print (stack[sp]) and sp ๏ƒŸ sp โ€“ 1 02 - OPR: RTN 0,0 Return operation (i.e. return from subroutine) OPR 0,1 NEG(-stack[sp]) OPR 0,2 ADD (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] + stack[sp + 1]) OPR 0,3 SUB (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] - stack[sp + 1]) OPR 0,4 MUL (sp ๏ƒŸsp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] * stack[sp + 1]) OPR 0,5 DIV (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] div stack[sp + 1]) OPR 0,6 ODD (stack[sp] ๏ƒŸ stack mod 2) or ord(odd(stack[sp])) OPR 0,7 MOD (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] mod stack[sp + 1]) OPR 0,8 EQL (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] = = stack[sp + 1]) OPR 0,9 NEQ (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] != stack[sp + 1]) OPR 0,10 LSS (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] < stack[sp + 1]) OPR 0,11 LEQ (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] <= stack[sp + 1]) OPR 0,12 GTR (sp ๏ƒŸ sp โ€“ 1 and stack[sp] ๏ƒŸ stack[sp] > stack[sp + 1])

stack[2] =0; stack[3] =0; Instructions The simulator of the virtual machine must be written in C. You must turn in by email: Source code, an example running in the virtual machine showing initial state of the stack and the stack state after the execution of each instruction. (see example) This example shows how to print the stack after the execution of each instruction: const n = 13; var i,h; procedure sub; const k = 7; var j,h; begin j:=n; i:=1; h:=k; end; begin i:=3; h:=0; call sub; end. INPUT FILE: It must be three integers and your program must print out: 7 0 10 7 0 2 6 0 5 we recommend to use as input format: 1 0 13 4 0 3 struct { 1 0 1 int op; /* opcode 4 1 3 int l; /* L 1 0 7 int m; /* M 4 0 4 }instruction; 2 0 0 6 0 5 1 0 3 4 0 3 1 0 0 4 0 4

2 0 0

OUTPUT FILE:

  1. Print out the execution of the program in the virtual machine, showing the stack and registers pc, bp, and sp:

    • 0 jmp 1) Print out the program
    • 1 jmp
    • 2 inc
    • 3 lit
    • 4 sto
    • 5 lit
    • 6 sto
    • 7 lit
    • 8 sto
    • 9 opr
  • 10 inc
  • 11 lit
  • 12 sto
  • 13 lit
  • 14 sto
  • 15 cal
  • 16 opr
  • Initial values pc bp sp stack - 0 jmp
  • 10 inc
  • 11 lit
  • 12 sto
  • 13 lit
  • 14 sto
  • 15 cal 0 2 2 6 5 0 0 0 3 0|
    • 2 inc 0 5 3 6 10 0 0 0 3 0|
    • 3 lit 0 13 4 6 11 0 0 0 3 0|
    • 4 sto 0 3 5 6 10 0 0 0 3 0|
    • 5 lit 0 1 6 6 11 0 0 0 3 0|
    • 6 sto 1 3 7 6 10 0 0 0 1 0|
    • 7 lit 0 7 8 6 11 0 0 0 1 0|
    • 8 sto 0 4 9 6 10 0 0 0 1 0|
    • 9 opr