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Homeworks 7 Pipelining.
Submission Requirements
● Type/write neatly for readability. ● Include a clear, specific question. ● Provide concrete, direct answers. ● Use data from provided slides.
PART 1 : Pipelining Introduction [10 points]
1. [5]List and briefly describe the five stages of the MIPS 5 - stage pipeline. What is the primary function of each stage? 1.1 Instruction Fetch (IF): It fetches the instruction from memory 1.2 Instruction Decode (ID): Decodes the instructions to identify the operation and operand. Reads the values from the source register file and generate the control signal for certain stages. 1.3 Execution (EX): Performs the logical operation, or shift using the ALU. Calculate the address for load and store instructions and evaluate the branch condition and target address for branch instructions. 1.4 Memory Access (MEM): For load instructions, it reads data from memory, and for store instruction, it writes data to memory and passes the result to the next stage. 1.5 Write Back (WB): It writes the results back to the destination register in the register file and is the very last stage for all instructions with results. 2. [5]What role do pipeline registers? ( True / False ) a. Pipeline registers store intermediate data and control signals between pipeline stages.(True) b. Pipeline registers enable simultaneous execution of multiple instructions in different stages by separating the stages.(True) c. Pipeline registers are responsible for detecting hazards and controlling forwarding to resolve data dependencies.(False) d. Pipeline registers help maintain the independence of each pipeline stage.(False)
PART 2 : Pipelining ( No Hazard ) [ 40 points ]
3. [10]How many instructions have been fully executed at the 100th clock cycle in the pipelined implementation of the MIPS processor? Assume there are NO hazards. Number of Instructions = 97 Show your work : After cycle 5, instructions are completed at 1 per clock cycle 100 - 5+1=9 6 Total Instructions completed=96+1= 4. [30] Pipeline Operation (5-stage MIPS pipeline). Consider the MIPS assemblylanguage code segment given below. (a) [10]Determine the number of clock cycles needed to execute this code segment on the pipelined implementation of the MIPS processor (5-stage pipeline). Assume that there are NO hazards (and no pipeline stalls). Show your works :
a)1 1 cycles
c IF ID EX MEM WB 1 I 2 I2^ I^1 3 I3^ I^2 I
4 I4 I3 I2 I
5 I5 I4 I3 I2 I
6 I6 I5 I4 I3 I
7 I7 I6 I5 I4 I
8 I7 I6 I5 I
9 I7^ I6^ I 10 I7^ I 11 I
(d) [10]Determine the number of clock cycles needed to execute a MIPS assembly language program consisting of 100 instructions on the 5 - stage MIPS pipeline. Assume that there are NO hazards (and no pipeline stalls).
- Number of Clock cycles= 100+4= 104
PART 3 : Pipelining ( Hazard ) [50 points]
1. [5] How many RAW data dependencies are there in the code segment given below? (a) 1 (b) 2 (c) 3 (d) 4 (e) More than 4. Show your works : I1, I2, dependencies $s I1,I3, dependencies $s I3,I 4 , dependencies $s I2,I5,dependences $s Answer: d) 4 dependencies 2. [5] Determine the number of clock cycles needed to properly execute the given code segment. Assume that the branch instruction is resolved in the MEM stage. Insert stalls as needed. Flush pipeline as needed. Assume that $t8 != $t9. # of Clock Cycles = 9 cycles Show your works : I1: add $s0, $s1, $s I2: add $s4, $s3, $s I3: add $s6, $s0, $s I4: add $t1, $s5, $t I5: add $t2, $t4, $s
After the 9th^ cycle, add $t0,$t1, $t2 is skipped because the branch is not taken [40] Data hazards and Forwarding Consider the MIPS assembly language code segment given below. The clock period for the MIPS pipelined processor is specified below for the processor with and without forwarding logic. c IF ID EX MEM WB 1 beq 2 add^ Beq 3 sub^ Add^ Beq 4 J^ Sub^ Add^ Beq 5 Add^ $a1^ J^ Sub^ Add^ Beq 6 Add^ $a1^ J^ Sub^ Add 7 Add$a1^ J^ Sub 8 Add^ $a1^ J 9 Add^ $a 10 11
(d) [10] Determine the ET of the given code segment on the processor without forwarding logic. CC IF ID EX MEM WB 1 I 2 I2^ I 3 I3^ I2^ I 4 Stall^ Stall^ I2^ I 5 Stall^ Stall^ Stall^ I2^ I 6 Stall^ I3^ I 7 Stall^ Stall^ I 8 Stall^ Stall^ Stall 9 Stall^ Stall^ Stall 10 11 …
ET: 9 CYCLES
TET: 250 psec* 9 cycles= 2250 psec
(a) [5] Determine the ET of the given code segment on the processor with forwarding logic. CC IF ID EX MEM WB 1 I^1
2 I2 I
2 I2 I
3 I3 I^2 I
3 I3 I^2 I
4 I3^ I2^ I 5 I3^ I2^ I 6 I3^ I 7 I Total Cycles: 7 cycles TET: 300psec*7cycles= 2100 psec (a) [5] Calculate the speedup achieved by adding forwarding logic to the pipelined processor. Speed up= (2250psec/2100psec)= 1.07= 7%
