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CSCE 491 â Capstone Computer Engineering Project Homework Assignments #1 and # Arithmetic Logic Unit (ALU) Design
The design for this ALU comes from the Tanenbaum, 4th^ ed., Computer Architecture , text. The gate-level schematic of the circuit is shown in Figure 1, and the truth table representation of the functionality to be supported in your design is shown in Figure 2.
Figures 1 & 2. The 1-bit ALU design specification.
We will be developing various design models of this combinational logic function block using the algorithmic state machine (ASM) method for modeling and designing finite state machines and their arithmetic data paths.
HW #1: Editing, Compiling, Simulating and Printing a Design Model
For this assignment, you will take the provided ASM design file printout, HW-01.pdf , and use it as your guide for entering your own version of the design. You will each be responsible for using flowHDL to enter this design as shown in the attached diagrams in the following figures. The design entry and verification consists of the following parts:
(1) Declare the signals and buses in the Bus Table, as shown in Figure 3, with one minor difference. Youâll need to declare all buses to have Element type = âwireâ instead of âcontextâ. (Note we are starting with a single-bit ALU unit in this assignment). The dialogue box for creating and modifying signals and buses in your design is shown in Figure 4. You access this through the Tables -> Bus Table pull down menu item.
Figure 3. Bus Table signal list.
Figure 4. Bus Table signal entry dialog box.
Figure 6. Two-state ASM thread for ALU.
(4) Attempt to compile the model, by selecting the âCompileâ menu option under the âToolsâ menu. Once you compile the model, you should get a dialog box indicating that you have no errors.
(5) If you get errors during the compilation, you should go to the state where errors are flagged (with a little âbugâ symbol, and click the object while holding down the âCTRLâ key (so, CTRL + Left Mouse). This will bring up and explanation of the error. NOTE: make sure the âCAPS LOCKâ key is not set.
On encountering an error, the messages will take some time to get used to, so if you see them, try to decipher what is being indicated as the problem. Usually, the cause of errors is that you are using signals in an assignment expression that have different bus widths, different signal types, or signal modes ( input , internal , internal_out , versus output ). Or, you may have a mismatch in the width of buses used as arguments to a macro and the bus that gets assigned the result. Or, the problem could be with parenthesis matching up. So, you may have to debug the design a bit. (However, the model does compile properly.)
(6) Once you have compiled the model, you will want to verify its correctness using the flowHDL model simulator. By setting stimuli for the design in the Bus Table, you can check the modelâs behavior by looking at the updated bus values in the Bus Table, or observe the signal values in the Waveform Viewer.
You need to select the âTools -> Wave Viewerâ to open the window for viewing waveforms. You need to select the âTools -> Simulateâ to open the simulator panel. Move the simulator panel to the upper left or right side of the screen.
Figure 7. Simulator cockpit.
To start simulation, you need to set a breakpoint on the reset state of the design. This is done by clicking on this state with the left mouse button. The state will change color (white) indicating that a breakpoint has been set. Then, you will click the âresetâ button on the simulator control panel, as shown in Figure 8. This will start the simulation clock, and pull the reset line, simulating the system reset. Then, you will press the âstepâ button, advancing the simulation by one clock cycle.
Figure 8. Canvas and Cockpit in Simulator mode.
Now, you can enter input values for (a) A and B operands, (b) ENA and ENB data input enable lines, (c) F0 and F1 function select lines, and (d) INV line, for a given test run. You will want to plan 4 separate test runs with these inputs, and write them into the Test Planning Worksheet template (see attached to this document or on the web page). After setting these values in the Bus Table, you will âstepâ through the design until the operation is completed. Figure 9 shows how these values are set in the Bus Table when flowHDL is in simulation mode.
After setting input values in the Bus Table, and as you âstepâ the simulation, you will see the waveform display advance along with the clock, showing the updated values of your signals. You will be looking for the specific output from the ALU,
(7) Now, once you get the model done, youâll want to do the following: (7a) enter your design information, through the âOptions -> Design -> Informationâ menu dialog. Enter a new design name (so spaces or non- alphanumeric, except â_â underline character, are not permitted), and specify your name and date and design version (which is v1.0). Use the information as shown in Figure 11. (7b) print your design, using the âFile -> Print-> Outputâ menu dialog. The default printer is the one in 1D39. You should select to print the entire design workspace (which will print the Canvas sheets and the Bus Table). Youâll probably want to set the format to âlandscapeâ instead of portrait for this design, and also reduce the size of the image to be printed. This can be done using the âFile -> Print -> Setupâ dialog. To print the design, you select the âFile -> Print -> Outputâ, which lets you print to the printer (âl39â in 1D39) or to a file (which can be printed from the Ghostscript application. (7c) print your waveform, using the dialog box accessed from the Wave Viewer (the âpiece of paperâ icon on the tool panel of the Wave Viewer). This dialog is shown in Figure 12. Each time you simulate, youâll want to rename the âHW01.wavâ file created after each simulation run and written into your working directory. Each waveform for each test will need to be printed out.
Figure 11. Design Information entry dialog box.
Figure 12. Waveform print dialog box.
(8) Finally, you will want to save your model, using the âFile -> Saveâ dialog box. Save the file as HW01.flo , and make sure you are writing it into your âcsce491â directory (which you should create). In fact, you will want to periodically save your model after you start creating it in flowHDL. Just like most software, it has been known to crash. So, save yourself some aggravation, save your model often during the editing process.
(9) Remember: You also need to preserve the waveform file after each simulation run and print each for inclusion in your assignment submission package. After you simulate each of your 4 test cases, youâll want to rename the existing file, HW01.wav , to HW01-1.wav for simulation results from test run #1, rename the second one as HW01-02.wav for simulation results from test run #2, and so on.
Before making your assignment submission, youâll want to check the Assignment Submission Guidelines, located on the course web page. Specifically, you will need to complete a cover page that has the Effort Distribution worksheet. I will want you to keep track of the time spent on each activity: (1) analysis & thinking about the problem, (2) editing, and (3) simulation & test planning. The other information we wonât use on these assignments.
Donât forget to answer the questions for Assignment #1, attached on separate pages.
Also, you will need to submit your assignments electronically.
instead of the more primitive gate-level formulation for addition). See the Lecture Notes to see how the ADD Macro works.
Youâll use the flowHDL editor to create the alternate ALU model, youâll check the design and compile it, and then youâll simulate it for 4 separate test cases to check for correct functionality and timing. You should use the same test data set that you created for HW #1.
This design doesnât meet the specification, as given in the schematic and truth table representations shown in Figures 1 and 2. Youâll need to make some changes to this model and submit to modified version, not the original version you have created. You will submit the simulation waveforms for simulating the initial version of HW02.flo , and the design model for the revised version, as HW02-v2.flo , changing the Design Information in Options -> Design -> Information dialog, as shown for Assignment #1. This modified version will be submitted, along with simulations for the original and for the modified versions.
You will submit the same set of deliverables as for Homework Assignment #1. So, youâll need to keep the waveform files, naming them as HW02-1.wav , HW02-2.wav , etc., for simulation of the first version, and HW02-v2-1.wav , HW02-v2-2.wav , etc., for simulation of the modified version of the design.
As with Assignment #1, donât forget to answer the questions about your modeling activity in Assignment #2, given in the following pages, just as you have done in Assignment #1.
STATEMENT OF PERSONAL RESPONSIBILTY: You can discuss the use of the tool in carrying out this and other assignments, but please do not discuss the solution of the design problemsâunless you are working with your team membersâas this will be considered cheating). I need to give everyone opportunity to get comfortable with the tool and the design methods, and this is how we will do it.
CSCE 491 â Capstone Computer Engineering Project Homework Assignments #1 & #2 ________________________ Arithmetic Logic Unit (ALU) Design Name / Date
You will turn this portion of the assignment in along with your design models, simulation output, Test Planning Worksheet, and Effort Distribution worksheet.
HW #1 Lab questions:
This design has two states, and operations scheduled on each state. Is there any problem with this design? Does it meet the function and timing requirements? Please explain.
If you see a problem with how the design has been carried out, how would you fix the
problem? How might you model the design differently, or change the model as entered,
so that the problem goes away?
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Can you edit the existing model we have created, HW-01.flo , and modify the model so that it functions correctly? If you can, re-create the deliverables, naming the new file as
