Homework - Memory: Cache Memory and Virtual Memory | CEG 320, Assignments of Computer Architecture and Organization

Material Type: Assignment; Class: Computer Organization; Subject: Computer Engineering; University: Wright State University-Main Campus; Term: Fall 2004;

Typology: Assignments

Pre 2010

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Cache Memory and Virtual Memory
1. Briefly (1 or 2 sentences) describe the LRU replacement algorithm.
Cache Memory
1. Name and describe the two types of locality of reference. Include examples.
2. Briefly (1 or 2 sentences) describe why locality of reference is an important concept with regard to
caching.
Virtual Memory
1. Briefly (1 or 2 sentences) describe the working set of a running program.
2. Briefly (1 or 2 sentences) describe thrashing.
3. Describe the purpose of the TLB.
CEG 320/520: Computer Organization and Assembly Language Programming
Fall, 2004
Homework: Memory updated: 3-nov-04
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Cache Memory and Virtual Memory

  1. Briefly (1 or 2 sentences) describe the LRU replacement algorithm.

Cache Memory

  1. Name and describe the two types of locality of reference. Include examples.
  2. Briefly (1 or 2 sentences) describe why locality of reference is an important concept with regard to caching.

Virtual Memory

  1. Briefly (1 or 2 sentences) describe the working set of a running program.
  2. Briefly (1 or 2 sentences) describe thrashing.
  3. Describe the purpose of the TLB.

CEG 320/520: Computer Organization and Assembly Language Programming

Fall, 2004 Homework: Memory updated: 3-nov-

Cache Performance Calculation

z hn = hit rate in level n cache z Cn = time to fetch a word from level n cache z M = time to access a word from main memory.

  1. Single Cache

1a. Without looking at your notes, try to derive the formula for determining the average access time for a word in a system with a single cache. Think about it!

t = h 1 C 1 + (1 - h 1 )M

1b. Assume the following values for a theoretical system containing an L1 cache.

Determine the average access time for a memory word in the described system.

  1. Three Caches

2a. Without looking at your notes, try to derive the formula for determining the average access time for a word in a system with three caches. Think about it!

t = h 1 C 1 + (1 - h 1 )(h 2 C 2 + (1 - h 2 )(h 3 C 3 + (1 - h 3 )M))

2b. Assume the following values for a theoretical system containing an L1, L2, and L3 cache.

Determine the average access time for a memory word in the described system.

Location Latency Hit Rate

L1 (on-chip) C^1 = 5ns^ h 1 = 50%

Main Memory M = 100ns h 3 = 100%

Location Latency Hit Rate

L1 (on-chip) C^1 = 5ns^ h 1 = 50%

L2 (on-chip) C^2 = 10ns^ h 2 = 75%

L3 (off-chip) C^3 = 35ns^ h 3 = 90%

Main Memory M = 100ns hM = 100%

3a. Suppose the system has a 2-way set associative cache. Now how is the address broken up? How many main memory blocks maps to each cache set?

3b. Describe how the system will check if a given word is currently in the cache. How many compares between the address and the tag field will be necessary?