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HW5 solutions Material Type: Notes; Professor: Theys; Class: Computer Architecture I: Logic and Computer Structures; Subject: Computer Science; University: University of Illinois - Chicago; Term: Fall 2012;
Typology: Study notes
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The following binary numbers have a sign in the leftmost position and, if negative, are in 2s complement form. Perform the indicated arithmetic operations and verify answers. Indicate whether overflow occurs for each computation.
a. [10] 100010 + 111110 Carries: 1 1 1 1 1 1 0 0 0 1 0
b. 䙰10䙱 001111 + 100010 Carries: 1 1 1 0 0 1 1 1 1
c. 䙰10䙱 101101 – 111011 The 2s complement of 111011 is 000101. Therefore we may do the addition 101101 + 000101, which is equivalent to the original subtraction. Carries: 1 1 1 1 0 1 1 0 1
Verifying the answer: The 2s complement of the 101101 is 010011 , which in decimal is 19. Therefore the decimal equivalent of 101101 is −19. The decimal equivalent of 000101 is 5. The 2s complement of 110010 is 001110 , which in decimal is 14. Therefore the decimal equivalent of 110010 is −14. Therefore we have −19 + 5 = −14.
d. 䙰10䙱 101100 – 001101 The 2s complement of 001101 is 110011. Therefore we may do the addition 101100 + 110011, which is equivalent to the original subtraction. Carries: 1 0 1 0 1 1 0 0
[30] Use Contraction beginning with a 4-bit adder with carry out to design a 4-bit increment-by-5 circuit with carry out that adds the binary value 0101 to its 4-bits input. The function to be implemented is ᡅ = ᠧ + 0101.
Solution:
The 4-bit adder that does increment-by-5 circuit with carry out is:
By using the contraction we are able to reduce the circuit to the following: