Input/Output Systems: Architectures, Transmission Modes, and Magnetic Disk Technology, Slides of Computer Architecture and Organization

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Chapter 7: IO

• Chapter7: IO – 1

CS140 Computer Organization

Chapter 7 Objectives

• Understand how I/O systems work, including I/O

methods and architectures.

• Become familiar with storage media, and the

differences in their respective formats.

• Understand how RAID improves disk performance and

reliability, and which RAID systems are most useful

today.

• Be familiar with emerging data storage technologies

and the barriers that remain to be overcome.

• Chapter7: IO – 2

7.2 I/O and Performance

• Sluggish I/O throughput can have a ripple effect, dragging down overall system performance. - This is especially true when virtual memory is involved.
• The fastest processor in the world is of little use if it spends most of its time waiting for data. - Chapter7: IO – 4

Not Enough

Memory

Put overflow of

Data and

Programs on Disk.

Slow

Machine

7.2 I/O and Performance

• Chapter7: IO – 5

7.3 Amdahl’s Law

EXAMPLE:

• On a large system, suppose we can upgrade a CPU to make it 50% faster for $10,000 or upgrade its disk drives for $7,000 to make them 250% faster.
• Processes spend 70% of their time running in the CPU and 30% of their time waiting for disk service.
• An upgrade of which component would offer the greater benefit for the lesser cost? - Chapter7: IO – 7

7.3 Amdahl’s Law

• The processor option offers a 130% speedup:
• And the disk drive option gives a 122% speedup:
• Each 1% of improvement for the processor costs $333, and for the disk a 1% improvement costs $318. - Chapter7: IO – 8 Should price/performance be your only concern?

EXAMPLE:

• On a large system, suppose we can upgrade a CPU to make it 50% faster

for $10,000 or upgrade its disk drives for $7,000 to make them 250%

faster.

• Processes spend 70% of their time running in the CPU and 30% of their

time waiting for disk service.

• An upgrade of which component would offer the greater benefit for the

lesser cost?

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7.4 I/O Architectures

This is a model I/O configuration.

• Chapter7: IO – 10

7.4 I/O Architectures - Buses

• Chapter7: IO – 11

Goal: Place data from

the disk into memory:

Steps in a bus operation:

1. Processor arbitrates for and sends request to the **PCI bus.

2. PCI passes request to** **SCSI controller.
3. SCSI controller arbitrates** for SCSI bus and then **passes request to disk.
4. Disk arbitrates for SCSI** bus and then sends data **back to SCSI controller.
5. The SCSI controller** arbitrates for control of the PCI bus and then makes request of bridge **controller (the chip set).
6. SCSI controller sends data** to memory.

7.4 I/O Architectures - Buses

• Chapter7: IO – 13

Bus Characteristics:

Bandwidth,

Response time,

Length,

Physical

Standardized?

7.4 I/O Architectures - Interfacing

• Chapter7: IO – 14

The Operating System has the job of talking to the hardware –

together they take responsibility for:

1. Allowing multiple programs using the processor to share the

IO,

2. Working with interrupts as a means of communicating

between the Processor and the IO,

3. Mechanisms that allow the processor to request IO

operations.

7.4 I/O Architectures

I/O can be controlled in four general ways.

• Programmed I/O reserves a register for each I/O device. Each register is continually polled to detect data arrival.
• Interrupt-Driven I/O allows the CPU to do other things until I/O is requested.
• Direct Memory Access (DMA) offloads I/O processing to a special-purpose chip that takes care of the details.
• Channel I/O uses dedicated I/O processors.
  • Chapter7: IO – 16

7.4 I/O Architectures

This is an idealized I/O subsystem that uses interrupts. Each device

connects its interrupt line to the interrupt controller.

• Chapter7: IO – 17

The controller

signals the

CPU when

any of the

interrupt lines

are asserted.

7.4 I/O Architectures

• Recall from Chapter 4 that in a system that uses interrupts, the status of the interrupt signal is checked at the top of the fetch- decode-execute cycle.
• The particular code that is executed whenever an interrupt occurs is determined by a set of addresses called interrupt vectors that are stored in low memory. PIC had only one at address = 4; bigger machines have many more.
• The system state is saved before the interrupt service routine is executed and is restored afterward. - Chapter7: IO – 19

7.4 I/O Architectures

This is a DMA

configuration.

Notice that the DMA

and the CPU share the

bus.

The DMA runs at a

higher priority and

steals memory cycles

from the CPU.

• Chapter7: IO – 20