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Semester I Examinations 2010/20 11 Exam Code(s) 4BN121, 4BP Exam(s) B.E. Degree Examination (Electrical & Electronic Engineering) B.E. Degree Examination (Electronic & Computer Engineering) Module Code(s) EE 315 Module(s) Semiconductor Technology Paper No. 1 Repeat Paper No External Examiner(s) Prof. G. W. Irwin Internal Examiner(s) Prof. G. Ó Laighin Dr. F Morgan Instructions: 1. Answer any three questions.
- All questions carry equal marks (20 marks).
- Figures are included in a handout. Submit the entire handout with your examination transcript.
- State any assumptions made in your answers.
- Answers must be presented in a neat and legible format. Include rough-work calculations. Provide adequate information in your answers to illustrate your understanding.
- MOSFET I-V equations:
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ds (^ )^ ^ .^ ox V^ gs Vth 2 2 Duration 2 hrs No. of Pages 3 (including cover page) Discipline Electrical & Electronic Engineering Course Co-ordinator(s) Dr. F. Morgan Requirements: Handout Y
(a) Illustrate the benefits in using CMOS logic by comparing CMOS behaviour with that of nMOS. [ 3 marks] (b) Figure 1a illustrates a cross-section through a CMOS inverter circuit. Include and label every element illustrated in Figure 1a. Indicate the function, material, and method of fabrication of each element. [6 marks] (c) Sketch and label the CMOS voltage transfer characteristic and associated current characteristic. Label and explain the various regions of operation. [4 marks] (d) For a CMOS transistor with parameters as follows: Vdd=3.5V,Vthpd= - Vthpu=0.7V Wpd/Lpd=2, Wpu/Lpu= Kpd =nCox = 20 A/V 2 , μn=2μp i. Calculate the CMOS inverter output voltage and the corresponding inverter current, when the inverter input voltage is 2.1V. ii. Calculate the CMOS inverter switching voltage Vinv. [7 marks] Clearly state (and verify) all assumptions. Question 2 (a) Figure 2a illustrates a circuit schematic for a FPGA Look Up Table (LUT). Label the main elements of this schematic and explain their operation. [4 marks] (b) Figure 2b illustrates a circuit schematic for a FPGA switch matrix. Explain the operation of the circuit, and draw a simplified representation of the switch matrix. [4 marks] (c) Design a CMOS combinational logic circuit to implement the following function: F = C.D.(B + C) Do not attempt any minimisation. [4 marks] (d) Draw the equivalent coloured mask stick diagram for the CMOS mask layout of Figure 2c (Input signals: A, B, C, D, E. Output signal F). [4 marks] (e) Draw the MOS transistor level circuit diagram for the implementation of Figure 2c and derive the Boolean description for the circuit. [4 marks]
(a) Figure 4a illustrates an example of a degating circuit. Label the unused inputs and explain how and why this circuit finds application. [ 2 marks] (b) Describe the problem of latchup in CMOS circuits and list three effects which can trigger latchup. Indicate a method used to avoid latchup occurrence. [ 4 marks] (c) Describe BiCMOS technology and list 3 advantages of BiCMOS technology over CMOS or Bipolar technology. [3 marks] (d) Describe the operation of the conventional BiCMOS inverter illustrated in Figure 4b. [ 4 marks] (e) Highlight and explain the impact of the following parameters on CMOS dynamic power. [3 marks] i. Clock frequency ii. Circuit capacitance iii. Supply voltage (f) A 150M gate CMOS transistor chip is fabricated using a 100nm, 1.2V process with the following parameters: 30M static logic transistors: average transistor width=12λ activity factor (α)=0. 120M memory transistors: average transistor width=4λ activity factor (α)=0. CMOS gate capacitance = 2.5 fF/μm i. Explain the meaning of activity factor. ii. Estimate the dynamic power consumption per MHz (neglecting wire capacitance and sort-circuit capacitance). (4 marks)
