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1
Instruction Execution
(Load and Store instructions)
ie := (
(op<4..0>= 1) : R[ra] ← M[disp], load register (ld) (op<4..0>= 2) : R[ra] ← M[rel], load register relative (ldr) (op<4..0>= 3) : M[disp] ← R[ra], store register (st) (op<4..0>= 4) : M[rel] ← R[ra], store register relative (str) (op<4..0>= 5) : R[ra] ← disp, load displacement address (la) (op<4..0>= 6) : R[ra] ← rel, load relative address (lar)
... ... ...
Other instructions go here
2
Instruction Execution
(Branch instructions)
ie := (
(op<4..0>= 8) : (cond : PC ← R[rb]), conditional branch (br) (op<4..0>= 9) : (R[ra] ← PC, cond : (PC ← R[rb]) ), branch and link (brl)
... ...
4
Instruction Execution
(Branch instructions)
ie := (
(op<4..0>= 8) : (cond : PC ← R[rb]), conditional branch (br) (op<4..0>= 9) : (R[ra] ← PC, cond : (PC ← R[rb]) ), branch and link (brl)
... ... cond := ( c3〈2..0〉=0 : 0, never c3〈2..0〉=1 : 1, always c3〈2..0〉=2 : R[rc]=0, if register is zero c3〈2..0〉=3 : R[rc]≠0, if register is nonzero c3〈2..0〉=4 : R[rc]〈 31 〉=0, if positive or zero c3〈2..0〉=5 : R[rc]〈 31 〉=1 ), if negative
This simply means that when c3<2..0> is equal to one of these six values, substitute the expression on the right hand side of the : in place of cond
5
Instruction Execution
(Arithmetic and Logical instructions)
ie := (
(op<4..0>=12) : R[ra] ← R[rb] + R[rc],
(op<4..0>=13) : R[ra] ← R[rb] + c2〈16..0〉 {sign extend},
(op<4..0>=14) : R[ra] ← R[rb] - R[rc],
(op<4..0>=15) : R[ra] ← - R[rc],
(op<4..0>=20) : R[ra] ← R[rb] & R[rc],
(op<4..0>=21) : R[ra] ← R[rb] & c2〈16..0〉 {sign extend},
(op<4..0>=22) : R[ra] ← R[rb] ∼ R[rc],
(op<4..0>=23) : R[ra] ← R[rb] ∼ c2〈16..0〉 {sign extend},
(op<4..0>=24) : R[ra] ←! R[rc],
7
Instruction Execution
(Shift instructions)
ie := (
(op<4..0>=26) : R[ra]〈31..0 〉 ← (n α 0) © R[rb] 〈31..n〉,
(op<4..0>=27) : R[ra]〈31..0 〉 ← (n α R[rb] 〈 31 〉) © R[rb] 〈31..n〉,
(op<4..0>=28) : R[ra]〈31..0 〉 ← R[rb] 〈31-n..0〉 © (n α 0),
(op<4..0>=29) : R[ra]〈31..0 〉 ← R[rb] 〈31-n..0〉 © R[rb]〈31..32-n 〉,
...
... where
n := ( (c3〈4..0〉=0) : R[rc],
(c3〈4..0〉≠0) : c3 〈4..0〉 ),
Notation: α means replication
© means concatenation Docsity.com
8
Instruction Execution
(Shift instructions)
ie := (
(op<4..0>=26) : R[ra]〈31..0 〉 ← (n α 0) © R[rb] 〈31..n〉,
(op<4..0>=27) : R[ra]〈31..0 〉 ← (n α R[rb] 〈 31 〉) © R[rb] 〈31..n〉,
(op<4..0>=28) : R[ra]〈31..0 〉 ← R[rb] 〈31-n..0〉 © (n α 0),
(op<4..0>=29) : R[ra]〈31..0 〉 ← R[rb] 〈31-n..0〉 © R[rb]〈31..32-n 〉,
... ...
Notation: α means replication
© means concatenation
where
n := ( (c3〈4..0〉=0) : R[rc],
(c3〈4..0〉≠0) : c3 〈4..0〉 ),
shr
shra
shl
shc
10
The basic D Flip-Flop
11
The basic D Flip-Flop
Q output
Active low
clear input
Clock input
Data input
Enable input
13
A 4-bit register: circuit
14
A 4-bit register: our symbol
Inputs
Outputs
Enable
Clock
16
A 4-bit register: waveforms
Outputs
Inputs
17
A 4-to-1 MUX: our symbol
(^3210)
output
Inputs
19
A 4-to-1 MUX: waveforms
20
Tri-state buffers: circuit symbol
ENABLE
Data Input Data Output
Data input
Enable Data output
X 0 Z
Don’t care
