Instruction Execution: Dynamic Scheduling I in ECE 412, Fall 2001, University of Illinois, Study notes of Computer Architecture and Organization

A lecture note from a university course on instruction execution, focusing on dynamic scheduling i using tomasulo's algorithm. Concepts such as dataflow, reservation station, renaming, retirement, and memory disambiguation. It explains the fundamental problem of taking instructions in the order prescribed by the programmer and the need for dynamic scheduling to execute instructions in parallel. The document also discusses data dependencies, dataflow concepts, and tomasulo's algorithm in detail.

Typology: Study notes

Pre 2010

Uploaded on 03/10/2009

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©S. J. Patel, 2001
ECE 412, Fall 2001, University of Illinois
Lecture 12
Instruction Execution :
Dynamic Scheduling I
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Download Instruction Execution: Dynamic Scheduling I in ECE 412, Fall 2001, University of Illinois and more Study notes Computer Architecture and Organization in PDF only on Docsity!

© S. J. Patel, 2001

Lecture 12

Instruction Execution :

Dynamic Scheduling I

© S. J. Patel, 2001

Outline

  • General concepts
    • dataflow
    • dynamic scheduling with Tomasulo’s

Algorithm

  • The P6 Execution Microarchitecture
  • Dynamic Scheduling Issues

© S. J. Patel, 2001

Dataflow Concepts

  1. MUL Ra, Rb -> Rm
  2. ADD Rc, Rd -> Rn
  3. SUB Rm, Rn -> Rx
  4. ADD Rr, Rs -> Rm
  5. ADD Rt, Rv -> Rn
  6. DIV Rm, Rn -> Ry

x = (a * b) - (c + d); y = (r + s) / (t + v);

Source Code Source Code (^) Machine CodeMachine Code

Dataflow Graph Dataflow Graph

© S. J. Patel, 2001

Dynamic Scheduling

  • Reservation Station
  • Renaming
  • Retirement/Recovery
  • Memory Disambiguation

Tomasulo’s Algorithm

© S. J. Patel, 2001

Data Dependencies

  • Read After Write
  • Write After Write
  • Write After Read
    1. MUL Ra, Rb -> Rm
    2. SUB Rm, Rn -> Rx
      1. MUL Ra, Rb -> Rm
      2. ADD Rr, Rs -> Rm
        1. SUB Rm, Rn -> Rx
        2. ADD Rr, Rs -> Rm

© S. J. Patel, 2001

Renaming

  • Objective: want to eliminate WAR and

WAW (false dependencies)

  • Renaming happens in program order
  • Renaming requires a table to map

between architectural registers and

physical registers

© S. J. Patel, 2001

Retirement using Reorder Buffer

Reorder Buffer Reorder Buffer

tail pointer

head pointer

Insts, in program order

An instruction that reaches the head and executes without exception can be safely retired

Values from Data Bus

•Flushing inflight instructions is easy – clear out RS and ROB

•Recovering RAT state is hard. That’s where the ROB comes in.

© S. J. Patel, 2001

Putting it all together

Register Alias Table

Reservation Stations

FU FU

Reorder Buffer

© S. J. Patel, 2001

Conceptual Memory Order Buffer

L/S L/S VV AddrAddr VV ValueValue

Loads/Stores in program order

  • Stores write into buffer and pass to memory only after they reach the head and are retired.

•What about loads?

  • Could go in order (highly conservative)

•Could wait until all previous unknown store addresses are known (not so conservative)

•Could go as soon as address is known (optimistic)