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ECE 190 Exam I Fall 2005
Tuesday, September 27th, 2005
- Be sure your exam booklet has 12 pages.
- Write your name at the top of each page.
- This is a closed book exam.
- You may not use a calculator.
- You are allowed one handwritten 8.5 x 11” sheet of notes.
- Absolutely no interaction between students is allowed.
- Show all of your work.
- Be sure to clearly indicate any assumptions that you make.
- **More challenging questions are marked with a *.
- Don’t panic, and good luck!
“A professor is one who talks in someone else’s sleep.” – W. H. Auden
Problem 1 20 points _______________________________
Problem 2 20 points _______________________________
Problem 3 20 points _______________________________
Problem 4 20 points _______________________________
Problem 5 20 points _______________________________
Total 100 points
Name:
Problem 1 (20 points): Short Answer
Part A (5 points): The IR (Instruction Register) holds the instruction that is to be executed. Given that the instruction bits can be held in the MDR, why is an IR necessary?
Part B (5 points): Consider the following LC-3 instruction (x3500 is the address at which the instruction is located):
x3500 LD R5, _____ ; we want to put the value x2BFF in register R
Given the above instruction, what is the range of memory addresses at which the value x2BFF can be stored such that the above instruction can be executed successfully?
Part C (5 points): A certain memory chip has a total of 2^32 bits and is 8-bit addressable. How many address bits must be specified when reading or writing a location on this chip?
Part D (5 points): What fraction of the range of numbers that can be represented with an N-bit 2’s complement data type can also be represented with an (N+1)-bit unsigned data type? (Justify your answer.)
Problem 3 (20 points): Combinational Logic
Part A (5 points): Write an expression for the function implemented by the CMOS circuit shown below.
Parts B and C refer to the circuit on the next page. The values A, B and R are in unsigned binary representation.
Part B (12 points): Connect the wires in the diagram in such a way that the four-bit value R is equal to A + B when SEL=0, and A – B when SEL=1. You may not add any additional gates. Ignore the output O for this part.
*****Part C** (3 points). Extend your answer to part B to generate output O=1 if an unsigned addition overflows or an unsigned subtraction underflows, and O=0 otherwise. You may use a single additional gate with either one or two inputs.
The NextA and NextB blocks are shown above. For both blocks, the S input is the current FSM state, the R input is the current fruit, and the N output is the next FSM state.
Part D (1 point): Find the next FSM state N 2 N 1 N 0 when a cherry is seen (R 1 R 0 =10).
Part E (2 points): The next FSM state takes one of two values when an orange is seen (R 1 R 0 =00). Fill in the table below specifying the next states as a function of the current state, using X to represent irrelevant inputs.
Part F (2 points): The next FSM state takes one of two values when a peach is seen (R 1 R 0 =01). Fill in the table below specifying the next states as a function of the current state, using X to represent irrelevant inputs.
Part G (4 points): Find the next FSM state when a lemon is seen (R 1 R 0 =11).
S 2 S 1 S 0 N 2 N 1 N 0
else
S 2 S 1 S 0 N 2 N 1 N 0
else
S 2 S 1 S 0 N 2 N 1 N 0
S 2 S 1 R 1 R 0
N 2 N 1 N 0
NextA
block
NextB
block
N 2 N 1 N 0
S 2 S 1 S 0
Part H (5 points) : Identify all winning combinations for this state machine and the amount paid for each. A winning combination is a minimal sequence of input combinations that takes the FSM from an arbitrary state into a particular payout state. It is minimal in the sense that no suffix of the combination suffices to reach the same payout state. For example, if the combination “cherry lemon” were such a sequence, neither “lemon cherry lemon” nor “orange cherry lemon” could be, since “cherry lemon” is a suffix of both.
Hint: work backwards from each state with non-zero payout.
Part C (8 points): Translate the code below into assembly language or RTL. For any PC-relative addresses, perform the calculation and write the resulting address rather than writing “PC + …”
***** Part D** (4 points): Explain what the code below does. A description that requires more than a few words is a good hint that you have the wrong idea. Hint: R0 and R1 are positive inputs, and R5 is the output.
Address Data Instruction (Assembly or RTL)
x4013 0000 001111111001
x4014 0001 101010100000
x4015 0101 011010100011
x4016 0001 100100111111
x4017 0000 101111111000
x4018 1111 000000110101
Address Data Instruction
x3000 0101 010000100000 AND R2, R0, #
x3001 0001 101010100001 ADD R5, R2, #
x3002 0001 011000100000 ADD R3, R0, #
x3003 0001 010010000101 ADD R2, R2, R
x3004 0001 011011111111 ADD R3, R3, #-
x3005 0000 001111111101 BRp #-
x3006 0001 101010100000 ADD R5, R2, #
x3007 0101 010010100000 AND R2, R2, #
x3008 0001 001001111111 ADD R1, R1, #-
x3009 0000 001111111000 BRp #-
x300A 1111 000000100101 TRAP x
Use this page for scratchwork.
