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Integrated Circuits (ICs)
In the 1950s, transistors and other electronic components were available only in individual packages. These discrete components were laid out on a circuit board and hand connected using separate wires. At that time, an electronic gate capable of storing a single binary bit of data cost more than $2. By comparison, in the early 1990s, enough gates to store 5,000 bits of data cost less than a cent. This vast reduction in price was primarily due to the invention
of the integrated circuit (IC). 1
A functional electronic circuit requires transistors, resistors, diodes, etc. and the connections between them. A monolithic integrated circuit (the "monolithic" qualifier is usually omitted) has all of these components formed on the surface layer of a sliver, or chip, of a single piece of semiconductor;
hence the term monolithic, meaning "seamless." Although a variety of semi-
conductor materials are available, the most commonly used is silicon, and integrated circuits are popularly known as "silicon chips." Unless otherwise noted, the remainder of these discussions will assume integrated circuits based on silicon as the semiconductor.
An O v e r v i e w of the Fabrication Process
The construction of integrated circuits requires one of most exacting pro- duction processes ever developed. The environment must be at least a thousand times cleaner than that of an operating theater, and impurities in materials have to be so low as to be measured in parts per billion, z The process begins with the growing of a single crystal of pure silicon in the form of a cylinder with a diameter that can be anywhere up to 300 mm. 3 The cylinder is cut into paper-
thin slices called wafers, which are approximately 0.2 mm thick (Figure 14-1).
1 In conversation, IC is pronounced by spelling it out as "I-C". 2 If you took a bag of flour and added a grain of salt, this would be impure by comparison. 3 This 300 mm value was true as of 2002. However, in 1995 (when the first edition of this tome hit the streets), the maximum diameter was 200 mm, so who knows what it will be in the future?
144 II C h a p t e r F o u r t e e n
25 mm to 3 0 0 mm
Cylindrical silicon
. 7 crystal
Wafer 0.2 mm
Figure 14-1. Creating silicon wafers
The thickness of the wafer is determined by the requirement for sufficient mechanical strength to allow it to be handled without damage. The actual thickness necessary for the creation of the electronic components is less than 10 gm (ten-millionths of a meter). After the wafers have been sliced from the cylinder, they are polished to a smoothness rivaling the finest mirrors. The most commonly used fabrication process is optical lithography, in which ultraviolet light (UV) is passed through a stencil-like 4 object called a photo- mask, or just mask for short. This square or rectangular mask carries patterns formed by areas that are either transparent or opaque to ultraviolet frequencies (similar in concept to a black and white photographic negative) and the result- ing image is projected onto the surface of the wafer. By means of some technical wizardry that we'll Ultraviolet radiation S O LI r o e
Each square corresl~onds to an individual integrated circuit
Wafer
I Mask i ii
4
consider in the next section, we can use the patterns of ultraviolet light to grow corresponding structures in the silicon. The simple patterns shown in the following diagrams were selected for reasons of clarity; in practice, a mask can contain millions of fine lines and geometric shapes (Figure 14-2). Each wafer can contain hundreds or thousands of identical integrated circuits. The pattern projected onto the wafer's surface corresponds to a
Figure 14-2. The opto-lithographic step-and-repeat process
4 The term "stencil" comes from the Middle English word stencelled, meaning "adorned brightly."
146 [] C h a p t e r F o u r t e e n
Organic resist Silicon Silicon dioxide (substrate)
Figure 14-5. Apply a layer of organic resist
Ultraviolet radiation source
" Mask
Organic resist
Silicon Silicon dioxide (substrate)
Figure 14-6. The exposed resist is degraded by the ultraviolet light
After the wafer has cooled, it is coated with a thin layer of organic resist, 5 which is first dried and then baked to form an impervious layer (Figure 14-5). A mask is created and ultraviolet light is applied. The ionizing ultraviolet radiation passes through the transparent areas of the mask into the resist, silicon dioxide, and silicon. The ultraviolet breaks down the molecular structure of the resist, but does not have any effect on the silicon dioxide or the pure silicon (Figure 14-6). As was previously noted, the small area of the mask shown here is associated with a single transistor. The full mask for an inte- grated circuit can consist of millions of similar patterns. After the area under the mask has been exposed, the wafer is moved, and the process is repeated until the pattern has been replicated across the wafer's entire surface, once for each inte- grated circuit. The wafer is then bathed in an organic solvent to dissolve the degraded resist. Thus, the
5 The term "organic" is used because this type of resist is a carbon-based compound, and carbon is the key element for life as we know it.
I n t e g r a t e d Circuits (ICs) 9 14 7
pattern on the mask has been transferred to a series of corresponding patterns in the resist (Figure 14-7). A process in which ultraviolet light passing through the transparent areas of the mask causes the resist to be degraded is
known as a positive-resist
process; negative-resist
processes are also available. In a negative-resist process, the ultraviolet radiation passing through the trans- parent areas of the mask is used to cure the resist, and the remaining uncured areas are then removed using an appropriate solvent. After the unwanted resist has been removed, the wafer undergoes a process
known as etching, in which
an appropriate solvent is
Organic resist Silicon (substrate) Silicon dioxide
Figure 14-7. The degraded resist is dissolved with an organic solvent
Organic resist Silicon Silicon dioxide (substrate) Figure 14-8. Etch the exposed silicon dioxide
used to dissolve any exposed silicon dioxide without having any effect on the organic resist or the pure silicon (Figure 14-8). The remaining resist is then removed using an appropriate solvent, and the wafer is placed in a high temperature oven where it is exposed to a gas contain- ing the selected dopant (a P-type dopant in this case). The atoms in the gas diffuse into the substrate resulting in a region of doped silicon (Figure 14-9). 6
6 In some processes, diffusion is augmented with ion implantation techniques, in which beams of ions
are directed at the wafer to alter the type and conductivity of the silicon in selected regions.
Integrated Circuits (ICs) 9 149
The end result is an NMOS transistor; a logic 1 on the track connected to
the gate will turn the
transistor ON, thereby enabling current to flow
between its source and drain
terminals. An equivalent PMOS transistor could have been formed by exchanging the P-type and N-type diffusion regions. By varying the structures
Metal track (drain) Metal track(gate)
Insulating layer of silicon dioxide Silicon (substrate)
Figure 14-11. Add the metalization (tracks)
Metal track (source)
created by the masks, components such as resistors and diodes can be fabricated at the same time as the transistors. The tracks are used to connect groups of transistors to form primitive logic gates and to connect groups of these gates to form more complex functions. An integrated circuit contains three distinct levels of conducting material:
the diffusion layer at the bottom, the polysilicon layers in the middle, and the
metalization layers at the top. In addition to forming components, the diffusion
layer may also be used to create embedded wires. Similarly, in addition to forming gate electrodes, the polysilicon may also be used to interconnect components. There may be several layers of polysilicon and several layers of metalization, with each pair of adjacent layers separated by an insulating layer of silicon dioxide. The layers of silicon dioxide are selectively etched with holes
known as vias, which allow connections to be made between the various
tracking layers. Early integrated circuits typically supported only two layers of metalization. The tracks on the first layer predominantly ran in a "North-South" direction, while the tracks on the second predominantly ran "East-West. ''7 As the number
7 In 2001, a group of companies announced a new chip interconnect concept called X Architecture (www.xinitiative.org) in which logic functions on chips are wired together using diagonal tracks (as opposed to traditional North-South and East-West tracking layers). Initial evaluations apparently show that this diagonal interconnect strategy can increase chip performance by 10% and reduce power consumption by 20%. However, it may take awhile before design tools and processes catch u p... watch this space?
150 9 C h a p t e r Fourteen
i
of transistors increased, engineers required more and more tracking layers.
The problem is that when a layer of insulating silicon dioxide is deposited
over a tracking layer, you end up with slight "bumps" where the tracks are
(like snow falling over a snoozing polar b e a r ~ y o u end up with a bump).
After a few tracking layers, the bumps are pronounced enough that you
can't continue. The answer is to re-planarize the wafer (smooth the bumps out)
after each tracking and silicon dioxide layer combo has been created. This is
achieved by means of a process called chemical mechanical polishing (CMP),
which returns the wafer to a smooth, flat surface before the next tracking layer
is added. With manufacturers using this process, high-end silicon chips could
support up to eight tracking layers by 2002.
Relatively large areas of aluminum called pads are constructed at the edges
of each integrated circuit for testing and connection purposes. Some of the pads
are used to supply power to the device, while the rest are used to provide input
and output signals (Figure 14-12).
The pads can be connected to the internal components using the diffusion,
polysilicon, or metalization layers. In a step known as overglassing, the entire surface of the wafer is coated with a final barrier layer (or passivation layer)
of silicon dioxide or silicon nitride, which provides physical protection for
the underlying circuits from moisture and other contaminants. One more
lithographic step is required to pattern holes in the barrier layer to allow
connections to be made to the pads. In some cases, additional metalization
may be deposited on the pads to raise them fractionally above the level of the
barrier layer. Augmenting the pads in this way is known as silicon bumping.
The entire fabrication process requires numerous lithographic steps, each
involving an individual mask
and layer of resist to
/ / ~ ~ ~ selectively expose
{>.///~ "{~7//~ different parts of
the wafer.
~Pads
Figure 14-12. Power and signal pads
152 9 C h a p t e r Fourteen
One of the criteria used when selecting the adhesive is its ability to conduct heat away from the die when the device is operating. A n automatic wire bonding tool connects the pads on the die to the leads on the lead frame with wire bonds finer than a human hair. 9 The whole assembly is then encapsulated in a block of plastic or epoxy (Figure 14-15).
Encapsu
bc
Figure 14-1 5. Wire bonding and encapsulation
A dimple or notch is formed at one end of the package so that the users will know which end is which. The unused parts of the lead frame are cut away and the device's leads, or pins, are shaped as required; these operations are usually performed at the same time (Figure 14-16).
N _ a..^ _ 1 _ ihape pins
Discard unus, lead frame
Figure 14-16. Discard unused lead frame and shape pins
9 Human hairs range in thickness from around 0.07 mm to 0.1 mm. A hair from a typical blond lady's head is approximately 0.075 mm (three quarters of one tenth of a millimeter) in diameter. By comparison, integrated circuit bonding wires are typically one-third this diameter, and they can be even thinner.
Integrated Circuits (ICs) 9 153
An individually packaged integrated circuit consists of the die and its connections to the external leads, all encapsulated in the protective package. The package protects the silicon from moisture and other impurities and helps to conduct heat away from the die when the device is operating. There is tremendous variety in the size and shape of packages. A rectangular device with pins on two sides, as illustrated here, is called a dual in-line (DIL) package. A standard 14-pin packaged device is approximately 18 mm long by 6.5 mm wide by 2.5 mm deep, and has 2.5 mm spaces between pins. An equiva- lent small outline package (SOP) could be as small as 4 mm long by 2 mm wide by 0.75 mm deep, and have 0.5 mm spaces between pins. Other packages can be square and have pins on all four sides, and some have an array of pins protruding from the base. The shapes into which the pins are bent depend on the way the device is intended to be mounted on a circuit board. The package described above has pins that are intended to go all the way through the circuit board using a mounting technique called lead through hole (LTH). By comparison, the packages associated with a technique called surface mount technology (SMT) have pins that are bent out flat, and which attach to one side (surface) of the circuit board (an example of this is shown in Chapter 18). It's important to note that the example shown above reflects a very simple packaging strategy for a device with very few pins. By 2002, some integrated circuits had as many as 1,000 pins (with 2,000- and 4,000-pin devices on the horizon). This multiplicity of pins requires a very different approach. In one technique known as solder bump bonding, for example, the pads on the die are not restricted to its periphery, but are instead located over the entire face of the die. A minute ball of solder is then attached to each pad, and the die is flipped over and attached to the package substrate (this is referred to as a "flip-chip" technique). Each pad on the die has a corresponding pad on the package substrate, and the package-die combo is heated so as to melt the solder balls and form good electrical connections between the die and the substrate (Figure 14-17). Eventually, the die will be encapsulated in some manner to protect it from the outside world. The package's substrate itself may be made out of the same material as a printed circuit board, or out of ceramic, or out of some even more esoteric material. Whatever its composition, the substrate will contain multiple
Integrated Circuits (ICs) 9 155
Integrated Circuits versus Discrete Components
The tracks linking components inside an integrated circuit have widths measured in fractions of a millionth of a meter and lengths measured in milli- meters. By comparison, the tracks linking components on a circuit board are orders of magnitude wider and have lengths measured in tens of centimeters. Thus, the transistors used to drive tracks inside an integrated circuit can be much smaller than those used to drive their circuit board equivalents, and smaller transistors use less power. Additionally, signals take a finite time to propagate down a track, so the shorter the track, the faster the signal. A single integrated circuit can contain tens (sometimes hundreds) of millions of transistors. A similar design based on discrete components would be tremendously more expensive in terms of price, size, operating speed, power requirements, and the time and effort required to design and manufacture th, system. Additionally, every solder joint on a circuit board is a potential source of failure, which affects the reliability of the design. Integrated circuits reduce the number of solder joints and hence improve the reliability of the system. In the past, an electronic system was typically composed of a number of integrated circuits, each with its own particular function (say a microprocessor, a communications function, some memory devices, etc.). For many of today's high-end applications, however, electronics engineers are combining all of these functions on a single device, which may be referred to as a system-on-chip(SoC).
Different Types of ICs
The first integrated circuit~a simple phase shift oscillator~was constructed in 1958.11 Since that time, a plethora of different device types have appeared on the scene. There are far too many different integrated circuit types for us to cover in this book, but some of the main categories~along with their approxi- mate dates of introduction~are shown in Figure 14-18. lz
11 The first integrated circuits typically contained around six transistors. By the latter half of the 1960s, devices containing around 100 transistors were reasonably typical. 12 The white portions of the timeline bars in this figure indicate that although early incarnations of these technologies may have been available, they perhaps hadn't been enthusiastically received during this period. For example, Xilinx introduced the world's first FPGA as early as 1984, but many design engineers didn't really become interested in these little rapscallions until the late 1980s.
156 9 C h a p t e r Fourteen 1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000 FPGAs PLDs ASICs Microprocessors
SRAMs & DRAMs
ICs (General) Transistors
Figure 14-18. Timeline of device introductions (dates are approximate)
Memory devices (in particular SRAMs and DRAMs) are introduced in Chapter 15; programmable integrated circuits (PLDs and FPGAs) are presented in Chapter 16; and application-specific integrated circuits (ASICs) are discussed in Chapter 17.
Technology Considerations Transistors are available in a variety of flavors called families or technologies. One of the first to be invented was the bipolarjunction transistor (BJT), which was the mainstay of the industry for many years. If bipolar transistors are connected together in a certain way, the resulting logic gates are classed as transistor-transistor logtc (TTL). An alternative method of connecting the same transistors results in logic gates classed as emitter-coupled logic (ECL). Another family called metal-oxide semiconductor field-effect transistors (MOSFETs) were invented some time after bipolar junction transistors. Complementary metal- oxide semiconductor (CMOS) logic gates are based on NMOS and PMOS MOFSETs connected together in a complementary manner. Logic gates constructed in TTL are fast and have strong drive capability, but consume a relatively large amount of power. Logic gates implemented in CMOS are a little slower than their TTL equivalents and have weaker drive capability, but their static (non-switching) power consumption is extremely low. Technology improvements continue to yield lower-power TTL devices and higher-speed CMOS devices. Logic gates built in ECL are substantially faster than their TTL counterparts, but consume correspondingly more power.
158 9 C h a p t e r Fourteen
This leads to the concept of an equivalent gate, whereby each type of logic function is assigned an equivalent gate value, and the relative complexity of an integrated circuit is judged by summing its equivalent gates. Unfortunately, the definition of an equivalent gate can vary, depending on whom one is talking to. A reasonably common convention is for a 2-input NAND to represent one equivalent gate. A more esoteric convention defines an ECL equivalent gate as being "one-eleventh the minimum logic required to implement a single-bit full-adder," while some vendors define an equivalent gate as being equal to an arbitrary number of transistors based on their own particular technology. The best policy is to establish a common frame of reference before releasing a firm grip on your hard-earned lucre. The acronyms SSI, MSI, LSI, VLSI, and ULSI represent Small-, Medium-, Large-, Very-Large-, and Ultra-Large-Scale Integration, respectively. By one convention, the number of gates represented by these terms are: SSI (1-12), MSI (13-99), LSI (100-999), VLSI ( 1,000-999,999), and ULSI ( 1,000, or more).
Device Geometries Integrated circuits are also categorized by their geometries, meaning the size of the structures created on the substrate. For example, a 1 ~m 13 CMOS device has structures that measure one-millionth of a meter. The structures typically embraced by this description are the width of the tracks and the length of the channel between the source and drain diffusion regions; the dimensions of other features are derived as ratios of these structures. Geometries are continuously shrinking as fabrication processes improve. In 1990, devices with 1 ~m geometries were considered to be state of the art, and many observers feared that the industry was approaching the limits of manufacturing technology, but geometries continued to shrink regardless: Anything below 0.5 ~m is referred to as deep-submicron (DSM), and at some point that isn't particularly well defined (or is defined differently by different people) we move into the realm of ultra-deep-submicron (UDSM).
13 The bt symbol stands for "micro" from the Greek micros, meaning "small" (hence the use of ~tP as an abbreviation for microprocessor). In the metric system, ~ stands for "one millionth part of," so 1 ~m means one millionth of a meter.
I n t e g r a t e d Circuits (ICs) 9! 59
1990 1.00 lttm 1992 0.80 lttm 1994 0.50 btm 1996 0.35 btm 1997 0.25 btm 1999 0.18 btm 2000 0.13 ~m 2001 0.10 lam 2002 0.09 btm
With devices whose geometries were 1 lam and higher, it was relatively easy to talk about them in
conversation. For example, one might say "I'm
working with a one micron technology." But things
started to get a little awkward when we dropped below 1 btm, because it's a bit of a pain to have to
keep on saying things like "zero point one-three
microns." For this reason, it's become common to
talk in terms of "nano," where one nano {short for "nanometer") equates to one thousandth of a m i c r o n ~ t h a t is, one thousandth of one millionth of a meter. Thus, when referring to a 0.13 btm technology, instead of mumbling
"zero point one-three microns," you would now proclaim "one hundred and thirty
nano." Of course both of these mean exactly the same thing, but if you want to
talk about this sort of stuff, it's best to use the vernacular of the day and present yourself as hip and trendy as opposed to an old fuddy-duddy from the last millennium. While smaller geometries result in lower power consumption and higher operating speeds, these benefits do not come without a price. Submicron logic gates exhibit extremely complex timing effects, which make corresponding demands on designers and design systems. Additionally, all materials are naturally radioactive to some extent, and the materials used to package inte- grated circuits can spontaneously release alpha particles. Devices with smaller geometries are more susceptible to the effects of noise, and the alpha decay in packages can cause corruption of the data being processed by deep-submicron logic gates. Deep-submicron technologies also suffer from a phenomenon
known as subatomic erosion or, more correctly, electromigration, in which the
structures in the silicon are eroded by the flow of electrons in much the same way as land is eroded by a river.
What Comes After Optical Lithography?
Although new techniques are constantly evolving, technologists can foresee the limits of miniaturization that can be practically achieved using optical lithography. These limits are ultimately dictated by the wavelength of ultraviolet
radiation. The technology has now passed from using standard ultraviolet (UV)
Integrated Circuits (ICs) 9! 61
Moore's Law
In 1965, Gordon Moore (who was to co-found Intel Corporation in 1968)
was preparing a speech that included a graph illustrating the growth in the
performance of memory ICs. While plotting this graph, Moore realized that
new generations of memory devices were released approximately every 18
months, and that each new generation of devices contained roughly twice
the capacity of its predecessor.
This observation subsequently became known as Moore's Law, and it has
been applied to a wide variety of electronics trends. These include the number
of transistors that can be constructed in a certain area of silicon (the number
doubles approximately every 18 months), the price per transistor (which follows
an inverse Moore's Law curve and halves approximately every 18 months), and
the performance of microprocessors (which again doubles approximately every
18 months).
Liquid crystal displays are often used for personal electronic appliances such as notebook computers. These displays are arranged as a matrix of points called pixels, each of which can be light or dark, and each of which is controlled by a transis- tor. Up until now, these displays have typically been fabricated as a sandwich of liquid crystal between two slices of glass. However, the following interest- ing little snippet was reported in the November 1994 edition of the IEEE Spectrum magazine: "Researchers at the French National Center f o r Scientific Research, in Thiais, say that they have developed an all-plastic, no-metal transistor. Using modern printing techniques, the group built up thin layers o f various materials
to construct paper-thin field-effect transistors, then employed plastic- like organic polymers and graphite inks to carry electricity. This development could lead to flexible computer screens that roll up like window shades." Personally the author has enough problems with his window shades spontaneously rolling up (which can offer one of life's unforgettable moments when parading in full glory in front of the bathroom mirror) without his computer screen doing the same thing. However, this opens the door to yet more science fiction predictions coming true in the foreseeable future: for example, comic books, newspapers, and textbooks with animated pictures and graphics. We truly do live in interesting times.
