INTERNAL MEMORY IN COA, Slides of Computer Architecture and Organization

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Internal Memory

Cell

Select Data in

Control

(a) Write

Cell

Select Sense

Figure 5.1 Memory Cell Operation

Control

(b) Read

+ Random Access Memory (RAM)

◼ RAM technology is divided into two technologies:

◼ Dynamic RAM (DRAM) ◼ Static RAM (SRAM)

◼ Dynamic RAM - DRAM

◼ Made with cells that store data as charge on capacitors

◼ Presence or absence of charge in a capacitor is interpreted as

a binary 1 or 0

◼ Requires periodic charge refreshing to maintain data storage

◼ The term dynamic refers to tendency of the stored charge to

leak away, even with power continuously applied

Address line Ground dc voltage Address line (b) Static RAM (SRAM) cell

Figure 5.2 Typical Memory Cell Structures

(a) Dynamic RAM (DRAM) cell Bit line B C 1 T 1 T 2 T 3 T 5 T 6 T 4 C 2 Bit line B Bit line B Transistor Ground Storage capacitor

+ DRAM Operation

• Address line active when bit read or written

◼ Transistor switch closed (current flows)

◼ Transistor switch open (current doesn’t flow)

• Analog Device
  • Capacitor can store any charge value within a range, a

threshold value will be used to interpret it.

+ DRAM Operation

• Write
  • Voltage to bit line - High for 1, low for 0
  • Then signal address line - transfers charge to

capacitor

• Read
  • Address line selected - transistor turns on
  • Charge from capacitor fed via bit line to sense

amplifier

• Compares with reference value to determine 0

or 1

• Capacitor charge must be restored

+ Static RAM

• Bits stored as on/off switches
• Four transistors, crossed connected, to produce stable logic state. ◼ More complex construction ◼ No charges to leak ◼ No refreshing needed when powered (dc voltage)
• Larger per bit
• More expensive
• Faster
• Used in Cache Memory
• Digital Device ◼ Uses flip-flops

SRAM versus DRAM

◼ Both volatile

◼ Power must be continuously supplied to the memory to preserve the bit values

◼ Dynamic cell

◼ Simpler to build, smaller ◼ More dense (smaller cells = more cells per unit area) ◼ Less expensive ◼ Requires the supporting refresh circuitry ◼ Tend to be favored for large memory requirements ◼ Used for main memory

◼ Static cell

◼ Faster ◼ Used for cache memory (both on and off chip) SRAM DRAM

+ Programmable ROM (PROM)

◼ Less expensive alternative

◼ Nonvolatile and may be written into only once

◼ Writing process is performed electrically and may be

performed by supplier or customer at a time later than the

original chip fabrication

◼ Special equipment is required for the writing process

◼ Provides flexibility and convenience

◼ Attractive for high volume production runs

Read-Mostly Memory EPROM Erasable programmable read-only memory Erasure process can be performed repeatedly More expensive than PROM but it has the advantage of the multiple update capability EEPROM Electrically erasable programmable read- only memory Can be written into at any time without erasing prior contents Combines the advantage of non-volatility with the flexibility of being updatable in place More expensive than EPROM Flash Memory Intermediate between EPROM and EEPROM in both cost and functionality Uses an electrical erasing technology, does not provide byte- level erasure Microchip is organized so that a section of memory cells are erased in a single action or “flash”

+ Error Correction

◼ Hard Failure

◼ Permanent physical defect ◼ Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1 ◼ Can be caused by: ◼ Harsh environmental abuse ◼ Manufacturing defects ◼ Wear

◼ Soft Error

◼ Random, non-destructive event that alters the contents of one or more memory cells ◼ No permanent damage to memory ◼ Can be caused by: ◼ Power supply problems

Advanced DRAM Organization ◼ One of the most critical system bottlenecks when using high-performance processors is the interface to main internal memory ◼ The traditional DRAM chip is constrained both by its internal architecture and by its interface to the processor’s memory bus ◼ A number of enhancements to the basic DRAM architecture have been explored ◼ The schemes that currently dominate the market are SDRAM and DDR-DRAM

SDRAM

RDRAM

DDR-DRAM

+ Double Data Rate SDRAM (DDR SDRAM)

◼ Developed by the JEDEC Solid State Technology Association

(Electronic Industries Alliance’s semiconductor-engineering-

standardization body)

◼ Numerous companies make DDR chips, which are widely

used in desktop computers and servers

◼ DDR achieves higher data rates in three ways:

◼ First, the data transfer is synchronized to both the rising and falling edge of the clock, rather than just the rising edge ◼ Second, DDR uses higher clock rate on the bus to increase the transfer rate ◼ Third, a buffering scheme is used

+ Flash Memory

◼ Used both for internal memory and external memory

applications

◼ First introduced in the mid-1980’s

◼ Is intermediate between EPROM and EEPROM in both cost and

functionality

◼ Uses an electrical erasing technology like EEPROM

◼ It is possible to erase just blocks of memory rather than an

entire chip

◼ Gets its name because the microchip is organized so that a

section of memory cells are erased in a single action

◼ Does not provide byte-level erasure

◼ Uses only one transistor per bit so it achieves the high density of

EPROM