interrupts, Study notes of Microprocessors

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Week 9

Interrupt Interface of 8088 and 8086

processors,

8259 Interrupt controller

Interrupt Mechanisms, Types, and Priority

INTERRUPT TYPES SHOWN WITH DECREASING PRIORITY

ORDER

• Reset
• Internal interrupts and exceptions
• Software interrupt
• Nonmaskable interrupt
• Hardware interrupt

All the interrupts are serviced on priority basis. The higher priority interrupt is served first and an active lower priority interrupt service is interrupted by a higher priority one. Lower priority interrupts will have to wait until their turns come. The section of program to which the control is passed called Interrupt- service routine (e.g. printer driver)

Interrupt Vector Table

Interrupt Vector Table

The Operation of Real Mode Interrupt

1. The contents of the flag registers are pushed onto the stack.
2. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single-step feature.
3. The contents of the code segment register (CS) is pushed onto the stack.
4. The contents of the instruction pointer (IP) is pushed onto the stack.
5. The interrupt vector contents are fetched, and then placed into both IP and CS so that the next instruction executes at the interrupt service procedure addressed by the interrupt vector.
6. While returning from the interrupt-service routine by the ins. IRET, flags return to their state prior to the interrupt and and operation restarts at the prior IP address. The return address (CS and IP) is not always the next instruction, with some interrupt types it is the current instruction.

Example

• At what address should vector 50, CS50, and IP50 be stored in memory?
• Each vector requires four bytes of memory
• Address = 50 x 4 = 200
• Converting to binary
  • 200 = 1100 1000b
  • Address = C8h
• IP50 is stored in 00C8h
• CS50 is stored in 00CAh

The Operation of Protected Mode Interrupt

1. Protected mode interrupts function like the real mode interrupts, except that the interrupt vector table is different.
2. It is replaced by the interrupt descriptor table.
3. Each entry is 8 byte long and there are 256 of them similar to the interrupt vectors of the real mode.
4. This table is located by the system at a memory location described by the Interrupt Descriptor Table Address Register (IDTR).

Interrupt instructions

External hardware-interrupt Interface

External hardware-interrupt Interface

External hardware-interrupt Interface

• Maximum mode hardware-interrupt interface:
  • The operation is similar with some differences.
  • Now bus status codes are used to generate some signals.
  • There is new signal called the bus priority lock signal LOCK¯. It is used to signal to the bus arbiter that the bus is busy.

External hardware-interrupt Interface

External hardware-interrupt Interface

External hardware-interrupt Sequence

• Only after the interrupt processing sequence is carried out, the interrupt acknowledge signal issued upon the result of checks.
• Note that fetching the values of CS and IP, and carrying out PUSH and POP operations take less number of bus cycles in 8086 than 8088 because of 16 bit data bus.