Xilinx ISE 9.1i Quick Start Tutorial: Creating a Counter Design, Study Guides, Projects, Research of Basic Electronics

Download Xilinx ISE 9.1i Quick Start Tutorial: Creating a Counter Design and more Study Guides, Projects, Research Basic Electronics in PDF only on Docsity!

R

ISE 9.1i Quick

Start Tutorial

ISE Quick Start Tutorial www.xilinx.com

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail- safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. Copyright © 1995-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

4 www.xilinx.com ISE Quick Start Tutorial

Preface: About This Tutorial

Preface: About This Tutorial

• ISE Quick Start Tutorial www.xilinx.com
  • Additional Resources
  • Getting Started ISE 9.1i Quick Start Tutorial
    • Software Requirements
    • Hardware Requirements
    • Starting the ISE Software
    • Accessing Help
  • Create a New Project
  • Create an HDL Source
    • Creating a VHDL Source
    • Using Language Templates (VHDL)
    • Final Editing of the VHDL Source
    • Creating a Verilog Source
    • Using Language Templates (Verilog)
    • Final Editing of the Verilog Source
    • Checking the Syntax of the New Counter Module
  • Design Simulation
    • Verifying Functionality using Behavioral Simulation
    • Simulating Design Functionality
  • Create Timing Constraints
    • Entering Timing Constraints
  • Implement Design and Verify Constraints
    • Implementing the Design
    • Assigning Pin Location Constraints
  • Reimplement Design and Verify Pin Locations
  • Download Design to the Spartan™-3 Demo Board

ISE Quick Start Tutorial www.xilinx.com 7

ISE 9.1i Quick Start Tutorial

The ISE 9.1i Quick Start Tutorial provides Xilinx PLD designers with a quick overview of the basic design process using ISE 9.1i. After you have completed the tutorial, you will have an understanding of how to create, verify, and implement a design. Note: This tutorial is designed for ISE 9.1i on Windows. This tutorial contains the following sections:

• “Getting Started”
• “Create a New Project”
• “Create an HDL Source”
• “Design Simulation”
• “Create Timing Constraints”
• “Implement Design and Verify Constraints”
• “Reimplement Design and Verify Pin Locations”
• “Download Design to the Spartan™-3 Demo Board” For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at: http://www.xilinx.com/support/techsup/tutorials/

Getting Started

Software Requirements

To use this tutorial, you must install the following software:

• ISE 9.1i For more information about installing Xilinx® software, see the ISE Release Notes and Installation Guide at: http://www.xilinx.com/support/software_manuals.htm.

Hardware Requirements

To use this tutorial, you must have the following hardware:

• Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board

8 www.xilinx.com ISE Quick Start Tutorial

Starting the ISE Software

To start ISE, double-click the desktop icon,

or start ISE from the Start menu by selecting: Start → All Programs → Xilinx ISE 9.1i → Project Navigator Note: Your start-up path is set during the installation process and may differ from the one above.

Accessing Help

At any time during the tutorial, you can access online help for additional information about the ISE software and related tools. To open Help, do either of the following:

• Press F1 to view Help for the specific tool or function that you have selected or highlighted.
• Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

Figure 1: ISE Help Topics

10 www.xilinx.com ISE Quick Start Tutorial

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete.

Create an HDL Source

In this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the “Creating a VHDL Source” section below, or skip to the “Creating a Verilog Source” section.

Creating a VHDL Source

Create a VHDL source file for the project as follows:

1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name counter.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:
7. Click Next , then Finish in the New Source Wizard - Summary dialog box to complete the new source file template.
8. Click Next , then Next , then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

Figure 3: Define Module

ISE Quick Start Tutorial www.xilinx.com 11

Create an HDL Source

Using Language Templates (VHDL)

The next step in creating the new source is to add the behavioral description for the counter. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design.

1. Place the cursor just below the begin statement within the counter architecture.
2. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible.
3. Using the “ + ” symbol, browse to the following code example: VHDL → Synthesis Constructs → Coding Examples → Counters → Binary → Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File , or select the Use Template in File toolbar button. This step copies the template into the counter source file.

Figure 4: New Project in ISE

ISE Quick Start Tutorial www.xilinx.com 13

Create an HDL Source

You have now created the VHDL source for the tutorial project. Skip past the Verilog sections below, and proceed to the “Checking the Syntax of the New Counter Module”section.

Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:

1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name counter.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:
7. Click Next , then Finish in the New Source Information dialog box to complete the new source file template.
8. Click Next , then Next , then Finish.

Figure 5: Define Module

14 www.xilinx.com ISE Quick Start Tutorial

The source file containing the counter module displays in the Workspace, and the counter displays in the Sources tab, as shown below:

Using Language Templates (Verilog)

The next step in creating the new source is to add the behavioral description for counter. Use a simple counter code example from the ISE Language Templates and customize it for the counter design.

1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
2. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile the Language Templates and the counter file by selecting Window → Tile Vertically to make them both visible.
3. Using the “ + ” symbol, browse to the following code example:

Figure 6: New Project in ISE

16 www.xilinx.com ISE Quick Start Tutorial

2. Select the counter design source in the Sources window to display the related processes in the Processes window.
3. Click the “ +” next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process. Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.
5. Close the HDL file.

Design Simulation

Verifying Functionality using Behavioral Simulation

Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows:

1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish.
7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: ♦ The counter must operate correctly with an input clock frequency = 25 MHz. ♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. ♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: ♦ Clock High Time: 20 ns. ♦ Clock Low Time: 20 ns. ♦ Input Setup Time: 10 ns. ♦ Output Valid Delay: 10 ns. ♦ Offset: 0 ns. ♦ Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. ♦ Initial Length of Test Bench: 1500 ns.

ISE Quick Start Tutorial www.xilinx.com 17

Design Simulation

Leave the default values in the remaining fields.

8. Click Finish to complete the timing initialization.
9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: ♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. ♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down.

Figure 7: Initialize Timing

ISE Quick Start Tutorial www.xilinx.com 19

Create Timing Constraints

The simulation waveform results will look like the following:

Note: You can ignore any rows that start with TX.

4. Verify that the counter is counting up and down as expected.
5. Close the simulation view. If you are prompted with the following message, “You have an active simulation open. Are you sure you want to close it?“, click Yes to continue. You have now completed simulation of your design using the ISE Simulator.

Create Timing Constraints

Specify the timing between the FPGA and its surrounding logic as well as the frequency the design must operate at internal to the FPGA. The timing is specified by entering constraints that guide the placement and routing of the design. It is recommended that you enter global constraints. The clock period constraint specifies the clock frequency at which your design must operate inside the FPGA. The offset constraints specify when to expect valid data at the FPGA inputs and when valid data will be available at the FPGA outputs.

Figure 10: Simulation Results

20 www.xilinx.com ISE Quick Start Tutorial

Entering Timing Constraints

To constrain the design do the following:

1. Select Synthesis/Implementation from the drop-down list in the Sources window.
2. Select the counter HDL source file.
3. Click the “ + ” sign next to the User Constraints processes group, and double-click the Create Timing Constraints process. ISE runs the Synthesis and Translate steps and automatically creates a User Constraints File (UCF). You will be prompted with the following message:
4. Click Yes to add the UCF file to your project. The counter.ucf file is added to your project and is visible in the Sources window. The Xilinx Constraints Editor opens automatically. Note: You can also create a UCF file for your project by selecting Project → Create New Source. In the next step, enter values in the fields associated with CLOCK in the Constraints Editor Global tab.
5. Select CLOCK in the Clock Net Name field, then select the Period toolbar button or double-click the empty Period field to display the Clock Period dialog box.

Figure 11: Prompt to Add UCF File to Project