CPSC 5155 Computer Architecture
Lab Assignment 5 Due Friday, November 30, 2007
The purpose of this lab is to implement two parts of the hardwired control unit for the Boz–5.
Specifically, the lab covers the Defer State and the Common Fetch Sequence.
Here is the circuit to be implemented for the Defer state.
Here is the circuit to be implemented for the Common Fetch Sequence.
Note that the circuits will have five inputs, each controlled by a switch. There will be
five switches in total: D, F, T0, T1, and T2. Use the toggle switches, not the momentary ones.
The outputs will be sent to a number of LED’s, one for each signal. Note that there are at least
two signals with multiple sources; PC B1 and MBR B2. Each source for the signal must
be placed as the input to an OR gate, the output of which drives the LED for the signal.
Exercise the lab by cycling through the two major states:
1. Set F = 1 (on), and then sequentially switch on T0, T1, and T2.
2. Set D = 1 (on), and then sequentially switch on T0, T1, and T2.
Ignore T3, as these circuits do not use that signal. Record what you see.
