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EEE241 Digital Logic Design

Digital Logic Design

EEE

Lab Manual

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Registration Number

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Instructor’s Name

EEE241 Digital Logic Design

1. Introduction This is the Lab Manual for EEE – 241 Digital Logic Design. The labs constitute 25 % of the total marks for this course. During the labs you will work in groups (no more than three students per group). You are required to complete the ‘Pre-Lab’ section of the lab before coming to the lab. You will be graded for this and the ‘In-Lab’ tasks during the in-lab viva. You will complete the ‘Post-Lab’ section of each lab before coming to the next week’s lab. You are not allowed to wander in the lab or consult other groups when performing experiments. Similarly, the lab reports must contain original efforts. CIIT has a zero tolerance anti-plagiarism policy. Apart from these weekly labs you will complete two projects. Lab Sessional I and Lab Sessional II will be conducted and graded as 10% and 15% marks, respectively. Final Project / Final Exam which will be graded as Lab Terminal. The grading policy is already discussed in the Course Description File.

EEE241 Digital Logic Design Version 4. January 2018 Dr. M. Faisal Siddiqui This is the fourth editable draft of EEE

• 241 lab manual. Some of the labs were improved. Pre-Lab, In-Lab and Post-Lab tasks were improved. Sequential circuit labs were re-modelled. Amendments had been made after the feedback from the DLD stream course and lab Instructors. For comments and suggestions please contact: [email protected] Version 5. August 2018 Dr. M. Faisal Siddiqui This is the fifth editable draft of EEE – 241 lab manual. Open ended labs were introduced in this version. For comments and suggestions please contact: [email protected]

EEE241 Digital Logic Design

2. Safety Precautions

• Be calm and relaxed, while working in lab.
• First check your measuring equipment.
• When working with voltages over 40 V or current over 10 A, there must be at least two people in the lab at all time.
• Keep the work area neat and clean.
• Be sure about the locations of fire extinguishers and first aid kit.
• No loose wires or metals pieces should be lying on the table or neat the circuit.
• Avoid using long wires, that may get in your way while making adjustments or changing leads.
• Be aware of bracelets, rings, and metal watch bands (if you are wearing any of them). Do not wear them near an energized circuit.
• When working with energize circuit use only one hand while keeping rest of your body away from conducting surfaces.
• Always check your circuit connections before power it ON.
• Always connect connection from load to power supply.
• Never use any faulty or damage equipment and tools.
• If an individual comes in contact with a live electrical conductor. o Do not touch the equipment, the cord, the person. o Disconnect the power source from the circuit breaker and pull out the plug using insulated material.

EEE241 Digital Logic Design

• Introduction 3. Table of Contents
• Acknowledgement
• History of Revision........................................................................................................................
• Safety Precautions
• Table of Contents
• Simulation LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus
  • Objective
  • Pre-Lab:..................................................................................................................................
  • In-Lab:..................................................................................................................................
  • Post-Lab Tasks:
  • Critical Analysis/Conclusion
• LAB #02: Boolean Function Implementation using Universal Gates
  • Objectives
  • Pre-Lab:................................................................................................................................
  • In lab:
  • Post-Lab:
  • Critical Analysis/Conclusion
• LAB #03: Introduction to Verilog and Simulation using XILINX ISE
  • Objective
  • Pre-Lab:................................................................................................................................
  • In-Lab:..................................................................................................................................
  • In-Lab Task 2:
  • Post-Lab:
  • Critical Analysis/Conclusion
• ICs/Verilog LAB #04: Design and Implementation of Boolean Functions by Standard Forms using
  • Objective
  • Pre-Lab:................................................................................................................................
  • Pre-Lab Tasks:
  • In-Lab Tasks:
  • Post-Lab Tasks:
  • Critical Analysis/Conclusion EEE241 Digital Logic Design
• LAB #05: Logic Minimization of Complex Functions using Automated Tools
  • Objective
  • Pre-Lab:................................................................................................................................
  • In-Lab:..................................................................................................................................
  • Post-Lab Tasks:
  • Critical Analysis/Conclusion
• LAB #06: Xilinx ISE Design Flow with FPGA
  • Objective
  • Pre-Lab:................................................................................................................................
  • In-Lab:..................................................................................................................................
  • In-Lab Task:
  • Post-Lab Task:
  • Critical Analysis/Conclusion
• 7. LAB #07: Design and Implementation of 𝒏 − 𝒃𝒊𝒕 Adder/Subtractor on FPGA...........
  • Objectives
  • Pre-Lab:................................................................................................................................
  • In-Lab Tasks:
  • Post-Lab:
  • Critical Analysis/Conclusion
• LAB #08: Design and Implementation of 𝒏 − 𝒃𝒊𝒕 Binary Multiplier on FPGA
  • Objective
  • Pre-Lab:................................................................................................................................
  • Pre-Lab Task
  • In-Lab Task 1: Implement 𝟒 − 𝒃𝒊𝒕 by 𝟐 − 𝒃𝒊𝒕 binary multiplier using ICs
  • In-Lab Task 2: Implement 𝟒 − 𝒃𝒊𝒕 by 𝟑 − 𝒃𝒊𝒕 binary multiplier on FPGA
  • Post-Lab Tasks:
  • Critical Analysis/Conclusion
• LAB #09: Design and Implementation of BCD to 7-Segment Decoder on FPGA
  • Objective
  • Pre-Lab:................................................................................................................................
  • common cathode 7-Segment display In-Lab Task 1: Test the functionality of a BCD to 7-Segment decoder IC (CD4511) with
  • (Nexys2) In-Lab Task 2: Design and implementation of a BCD to 7-Segment decoder on FPGA
  • Post-Lab Task:
  • Critical Analysis/Conclusion
• Machine...................................................................................................................................... Lab #10: Design and Implementation of a Sequence Detector using Mealy/Moore
  • Objective
  • Pre-Lab:..............................................................................................................................
  • In-Lab: Design and Implementation of a Sequence Detector using Mealy Machine
  • Sequence: _________________________________
  • Post-Lab Tasks:
  • Critical Analysis/Conclusion
• LAB #11: Implementation of a BCD Counter with Control Inputs on FPGA
  • Objective
  • Pre-Lab:..............................................................................................................................
  • In-Lab: Implementation of a BCD Counter with control inputs on FPGA........................
  • Post-Lab Task:
  • Critical Analysis/Conclusion
• Lab #12: Implementation of a Special Shift Register on FPGA
  • Objective
  • Pre-Lab:..............................................................................................................................
  • In-Lab Tasks:
  • Post-Lab Task:
  • Critical Analysis/Conclusion

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

AND gate:

Figure 1. 1 : AND gate Table 1. 1 : Truth Table of 2 input AND gate 𝑨 𝑩 𝑭 = 𝑨. 𝑩 0 0 0 0 1 0 1 0 0 1 1 1 The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB.

OR gate:

Figure 1. 2 : OR gate Table 1. 2 : Truth Table of 2 input OR gate 𝑨 𝑩 𝑭 = 𝑨 + 𝑩 0 0 0 0 1 1 1 0 1 1 1 1 The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation.

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

NOT gate

Figure 1. 3 : NOT gate Table 1. 3 : Truth Table of NOT gate 𝑨 (^) 𝑭 = 𝑨̅ 0 1 1 0 The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter.

NAND gate

Figure 1. 4 : NAND gate Table 1. 4 : Truth Table of 2 input NAND gate 𝑨 𝑩 𝑭 = 𝑨̅̅̅ .̅ 𝑩̅̅ 0 0 1 0 1 1 1 0 1 1 1 0 This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The output of NAND gate is high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

XNOR gate

Figure 1. 7 : XNOR gate Table 1. 7 : Truth Table of 2 input XNOR gate 𝑨 𝑩 𝑭 = 𝑨̅̅̅ ⊕̅̅̅ ̅𝑩̅̅ 0 0 1 0 1 0 1 0 0 1 1 1 The ' Exclusive-NOR' gate circuit does the opposite to the XOR gate. It will give a high output if even number of inputs are high. The symbol is an XOR gate with a small circle on the output. The small circle represents inversion. Digital systems are said to be constructed by using logic gates. These gates are AND, OR, NOT, NAND, NOR, XOR and XNOR. Logic gate ICs are available in different packages and technologies. Two main classifications are as below:

1. 74 Series TTL Logic ICs
2. 4000 Series CMOS Logic ICs 74 series is TTL (Transistor-Transistor Logic) based integrated circuits family. Power rating for 74 series is 5 to 5.5Volts. This circuitry has fast speed but requires more power than later families. The Pin configuration of basic gates 2-input ICs for 74 Series is given in Figure 1.8: Figure 1. 8 : TTL ICs’ pin configuration

XNOR

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation Figure 1.8 shows the 4000 series is CMOS (complementary metal oxide semiconductors) based integrated circuits. Power ratings are 3V to 15 Volts. CMOS circuitry consumes low power, but it is not fast as compared to TTL. 7 Figure 1. 9 : Different CMOS ICs’ pin configuration

Quad 2-input gates

The ICs available in Lab to perform the Tasks are listed below: In-Lab:

Part 1: Basic Logic Gate Integrated Circuits (ICs)

Equipment Required

• KL-31001 Digital Logic Lab
• Logic gates ICs o 4001 quad 2-input NOR o 4011 quad 2-input NAND o 4070 quad 2-input XOR o 4071 quad 2-input OR o 4077 quad 2-input XNOR o 4081 quad 2-input AND o 4069 Six Inverting Buffer NOT

Procedure

1. Place the IC on the breadboard as shown in the Figure 1.10;
2. Using the power supply available at KL-31001 Digital Logic Lab trainer, connect pin7 (Ground) and pin 1 4 (Vcc) to power up IC.

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation Table 1. 9 : Observation Table for NOT gate

INPUT OUTPUT

Part 2 - Proteus (Simulation Software)

Proteus has many features to generate both analog and digital results over a virtual environment. However, this lab will focus on tools that will be used in digital schematic designs and verification of basic logic gates.

Procedure

The Proteus software for simulation is installed in Digital Design Lab. Please follow the details below to figure out the usage of Proteus tools and process of simulation. Figure 1. 11 : Interface of Proteus software window

Parts Browsing:

Proteus has many models of electronic equipment such as logic gates, many kinds of switches and basic electronic devices. The equipment can be placed by clicking on it and then a new window will pop-up as shown in Figure 1.12.

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation

Finding Steps:

1. Type information of device such as “OR gate” in “ Keywords’ box.
2. If some specific category is known, the device can narrow on focusing by selecting catalogue in the “ Category” box.
3. After the information is entered, the list of related devices will appear in the “ Results” window, so that needed device can be chosen and then click “OK” button to confirm selection in Figure 1. 13. Figure 1. 12 : Pick Devices window in Proteus

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation Figure 1. 14 : Power supplies window in Proteus (^) Figure 1. 15 : Terminals window in Proteus

Logic State:

In addition, there is another input that usually used in the digital circuit, but it does not exist in the real world as an equipment it is called as “LOGIC STATE”. It can be found in the picking part section (type logic state and pick it as shown in Figure 1.16). Figure 1. 16 : Logic State in Proteus

Placing Equipment:

Selecting all devices needed to be placed on the circuit window (Gray window) and make the required connections. It can be done by following steps:

1. Click on and select the first device that will be placed.
2. Place mouse wherever the device is preferred to place and then click the left button of the mouse. The device will be placed, if it is needed to be moved, click the right button of the mouse on the device symbol to select the mouse. Then hold this device with the left mouse button and move it to any desired place (Figure 1.17).

LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation Figure 1. 17 : Placing the devices in Proteus To make the connections between the devices, click on the source pin of a device and then move the cursor to destination pin of a device. In this step, the pink line will appear, and it will be a wire of the circuit after clicking the mouse on the destination pin of the circuit (as shown in Figure 1. 18 ). Digi Figure 1. 18 : Making connection between devices to make a circuit After wiring all devices and connect all inputs according to the circuit, the simulation is ready to run by clicking on Play button and stop button is used to stop the simulation.

3. Logic probe or LED can be used to observe the output state.