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Laboratory Assignment on Altera DE2 Board Cyclone II FPGA Programming using VHDL, Lab Reports of Microprocessors

Purdue University GlobalMicroprocessors

This laboratory assignment focuses on utilizing behavioral vhdl modeling and ieee packages to implement an 8-bit pmips alu system and an 8 x 8-bit pmips bypassed arf system on the altera de2 board. The objectives include fpga implementation, synthesis, and understanding timing considerations for digital systems. The assignment also covers programming the de2 fpga board and demonstrating the functionality of the systems.

Typology: Lab Reports

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Uploaded on 08/06/2009

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LABORATORY ASSIGNMENT # 7
Altera DE2 Board Cyclone II FPGA Programming
The 8-bit pMIPS ALU DE2 System and
The 8 x 8-bit pMIPS Bypassed ARF DE2 System
Spring 2009
Due Date: April 6
th
, 2009
ECE 371: Microprocessor Systems Laboratory
Department of Electrical and Computer Engineering
School of Engineering, Mathematics, & Sciences
Purdue University – Calumet
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Download Laboratory Assignment on Altera DE2 Board Cyclone II FPGA Programming using VHDL and more Lab Reports Microprocessors in PDF only on Docsity!

LABORATORY ASSIGNMENT # 7

Altera DE2 Board Cyclone II FPGA Programming

The 8-bit pMIPS ALU DE2 System and

The 8 x 8-bit pMIPS Bypassed ARF DE2 System

Spring 2009

Due Date: April 6th, 2009

ECE 371: Microprocessor Systems Laboratory

Department of Electrical and Computer Engineering

School of Engineering, Mathematics, & Sciences

Purdue University – Calumet

OBJECTIVES

Objectives of this laboratory assignment are to:

  • Utilize behavioral VHDL modeling and IEEE packages to implement an 8-bit pMIPS ALU System
  • Utilize behavioral VHDL modeling and IEEE packages to implement an 8 x 8-bit pMIPS Bypassed ARF System
  • Introduce FPGA implementation in the context of complex combinational and sequential digital systems
  • Understand how to synthesize a design on the DE2 FPGA Board
  • Understand several timing considerations when implementing digital systems

REFERENCES

DE2 Board Information and Cyclone II FPGA Architecture

[1] Altera DE2 Board User Manual. Chapter 4: Using the DE2 Board. Version 1.4 (2006). Link: ftp://ftp.altera.com/up/pub/Webdocs/DE2_UserManual.pdf [2] Altera Cyclone II Handbook: Chapter 2: Cyclone II Architecture. Version 3.1 (February 2007). Link: http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf

Cyclone II FPGA Synthesis, Timing, and Programming Tutorials and Tools

[3] Altera VHDL Tutorial: Introduction to the Quartus II Software Link: ftp://ftp.altera.com/up/pub/Tutorials/DE2/Digital_Logic/tut_quartus_intro_vhdl.pdf [4] Altera VHDL Tutorial: Timing Considerations Link: ftp://ftp.altera.com/up/pub/Tutorials/DE2/Digital_Logic/tut_timing_vhdl.pdf [5] Altera Quartus II Handbook. Volume 3. Chapter 9: Quartus II Integrated Synthesis. Ver. 9.0 (March 2009) Link: http://www.altera.com/literature/hb/qts/qts_qii51008.pdf [6] Altera Quartus II Handbook. Volume 3. Chapter 10: Quartus II Classic Timing Analyzer. Ver. 9.0 (March 2009) Link: http://www.altera.com/literature/hb/qts/qts_qii53004.pdf [7] DE2 Pin Assignment Comma Separated File (.csv file) : DE2 CD-ROM Ver. 1.2. Link: ftp://ftp.altera.com/up/pub/de2/DE2_System_v1.2.zip

PRE-LABORATORY ACTIVITIES

Thoroughly review documents [1], [2], [3], [4], [5], and [6] provided in the Reference section of this laboratory document before staring this laboratory assignment.

BACKGROUND

The 8-bit pMIPS ALU DE2 Board Cyclone II FPGA System

Shown in Figure 1 is the 8-bit pMIPS ALU DE2 Board Cyclone II FPGA system. The system consists of an 8-bit pMIPS ALU and surrounding I/O hardware that interfaces the ALU to the DE2 board’s switches, pushbuttons, 7-segment displays, and internal clocks.

I/O Port DE2 I/O Device DE2 .csv Name Logic Description Clock (^) 27 MHz Internal Clock CLOCK_27 (^) Internal DE2 Signal Reset (^) Switch 17 SW[17] (^) Up: Logic High A[7:0] (^) Switches 15-8 SW[15:8] (^) Up: Logic High B[7:0] (^) Switches 7-0 SW[7:0] (^) Up: Logic High ALUOp[3:0] (^) Keys 3-0 KEY[3:0] (^) Pressed: Logic Low Result[7:4] (^) 7-seg Display 1 HEX1[6:0] (^) Negative Logic Result[3:0] (^) 7-seg Display 0 HEX0[6:0] (^) Negative Logic Z (^) Green LED 0 LEDG[0] (^) Positive Logic C (^) Green LED 1 LEDG[1] (^) Positive Logic V (^) Green LED 2 LEDG[2] (^) Positive Logic

Table 2: The 8-bit pMIPS ALU Pin Assignment Scheme

The 8-bit pMIPS 8 x 8-bit Bypassed ARF DE2 Board Cyclone II FPGA System

Shown in Figure 2 is the 8 x 8-bit pMIPS bypassed ARF DE2 Board Cyclone II FPGA system. The system consists of an 8 x 8-bit pMIPS bypassed ARF and surrounding I/O hardware that interfaces the ARF to the DE2 board’s switches, pushbuttons, 7-segment displays, and internal clocks.

Figure 2: The 8 x 8-bit pMIPS Bypassed ARF System Specific for the Altera DE2 Board

The 8 x 8-bit pMIPS bypassed ARF module shown above is functionally equivalent to the 32 x n-bit bypassed pMIPS ARF implemented as part of laboratory assignment #6. However, in order to simplify programming and I/O interfacing on the Altera DE2 board, the original 32 x n-bit bypassed pMIPS ARF designed in laboratory #6 cannot be used. As a result, this laboratory assignment provides an excellent opportunity to continue practicing behavioral VHDL modeling of memory-based circuits by implementing a behavioral 8 x 8-bit pMIPS bypassed ARF. For reference, the functional specification of the 8 x 8-bit pMIPS bypassed ARF is repeated below.

  1. Contains thirty-two pMIPS ISA general purpose registers (GPRs).
  2. Two registers can be asynchronously read at any given time by supplying two register addresses.
  3. One register at a time can be synchronously written on the positive edge of the clock at by supplying one register address and asserting a write enable signal.
  4. If a register is read and written in the same cycle, the new value appears at the output of the ARF.
  5. Register $R0 always contains the value 0x0 (it is hardwired to zero).
  6. Upon synchronous reset, all registers should contain the value of 0x.

Table 3 below describes the DE2 I/O devices that will be used to interface with the 8 x 8-bit pMIPS bypassed ARF DE system.

I/O Port DE2 I/O Device DE2 .csv Name Logic Description Clock (^) 27 MHz Internal Clock CLOCK_27 (^) Internal DE2 Signal WriteEn (^) Key 3 KEY[3] (^) Pressed: Logic Low Reset (^) Key 2 KEY[2] (^) Pressed: Logic Low Reg1Addr[2:0] (^) Switches 16 to 14 SW[16:14] (^) Up: Logic High Reg2Addr[2:0] (^) Switches 13 to 11 SW[13:11] (^) Up: Logic High RegWriteAddr[2:0] (^) Switches 10 to 8 SW[10:8] (^) Up: Logic High RegWriteData[7:0] (^) Switches 7 to 0 SW[7:0] (^) Up: Logic High Reg1Data[7:4] (^) 7-Segment Display 3 HEX3[6:0] (^) Negative Logic Reg1Data[3:0] (^) 7-Segment Display 2 HEX2[6:0] (^) Negative Logic Reg2Data[7:4] (^) 7 Segment Display 1 HEX1[6:0] (^) Negative Logic Reg2Data[3:0] (^) 7 Segment Display 0 HEX0[6:0] (^) Negative Logic

Table 3: The 8 x 8-bit pMIPS Bypassed ARF Pin Assignment Scheme

PROCEDURE

Task 1

(a) Implement, functionally simulate, and validate the 8-bit pMIPS ALU DE2 system using a combination of dataflow, structural, and behavioral architecture modeling in VHDL. Use the interface specification defined in Table 4.

Port Mode Type Size Description CLOCK_27 (^) Input STD_LOGIC (^) 1-bit Synchronizing clock signal SW[17] (^) Input STD_LOGIC (^) 1-bit Synchronous reset. Resets registers to 0x0. SW[15:8] (^) Input STD_LOGIC_VECTOR (^) 8-bits Switches corresponding to operand A SW[7:0] (^) Input STD_LOGIC_VECTOR (^) 8-bits Switches corresponding to operand B KEY[3:0] (^) Input STD_LOGIC_VECTOR (^) 4-bits The push-buttons that represent ALUOp HEX1[6:0] (^) Outputs STD_LOGIC_VECTOR (^) 7-bits 7-segment used to display Result[7:4] HEX0[6:0] (^) Outputs STD_LOGIC_VECTOR (^) 7-bits 7-segment used to display the R esult[3:0] LEDG[2:0] (^) Output STD_LOGIC_VECTOR (^) 3-bits Green LEDs used to display Flags { V, C, Z }

Table 4: Interface Specification for the 8-bit pMIPS ALU System

ALU Operation ALUOp[3:0]^ A[7:0]^ B[7:0]^ Result[7:0]^ C^ V^ Z^ Validated AND 0000 0x00 0xF0 (^) Yes / No OR 0001 0xFF 0x55 (^) Yes / No XOR 0010 0xFF 0x55 (^) Yes / No NOR 0011 0x00 0x00 (^) Yes / No ADD 0101 0x10 0x35 (^) Yes / No ADD 0101 0x7F 0x35 (^) Yes / No ADD 0101 0x0A 0xFF (^) Yes / No ADD 0101 0xFF 0x0A (^) Yes / No ADD 0101 0x80 0xFF (^) Yes / No ADD 0101 0xFF 0xF8 (^) Yes / No ADDU 0100 0x10 0x35 (^) Yes / No ADDU 0100 0x7F 0x35 (^) Yes / No SUB 0111 0x0A 0x14 (^) Yes / No SUB 0111 0x0A 0xE2 (^) Yes / No SUB 0111 0x73 0xDF (^) Yes / No SUB 0111 0xF6 0x1E (^) Yes / No SUB 0111 0xF6 0x7F (^) Yes / No SUB 0111 0xEC 0xE2 (^) Yes / No SUBU 0110 0x14 0x0A (^) Yes / No SUBU 0110 0x07 0x05 (^) Yes / No SLT 1011 0x07 0x05 (^) Yes / No SLT 1011 0x94 0xA1 (^) Yes / No SLTU 1010 0x07 0x05 (^) Yes / No SLTU 1010 0x94 0xA1 (^) Yes / No SLL 1100 0x01 0xFF (^) Yes / No SLL 1100 0x02 0xFF (^) Yes / No SLL 1100 0x03 0xFF (^) Yes / No SLL 1100 0x04 0xFF (^) Yes / No SRL 1110 0x01 0xFF (^) Yes / No SRL 1110 0x02 0xFF (^) Yes / No SRL 1110 0x03 0xFF (^) Yes / No SRL 1110 0x04 0xFF (^) Yes / No SRA 1111 0x01 0xF0 (^) Yes / No SRA 1111 0x02 0xF0 (^) Yes / No SRA 1111 0x03 0xF0 (^) Yes / No SRA 1111 0x04 0xF0 (^) Yes / No SRA 1111 0x01 0x7F (^) Yes / No SRA 1111 0x02 0x7F (^) Yes / No SRA 1111 0x03 0x7F (^) Yes / No SRA 1111 0x04 0x7F (^) Yes / No

Table 5: The 8-bit pMIPS ALU Validation Plan

Task 2

(a) Implement, functionally simulate, and validate the 8 x 8-bit pMIPS bypassed ARF DE2 system using a combination of structural and behavioral architecture modeling in VHDL. The 8 x 8-bit ARF DE2 system interface specification is defined in given in Table 6.

Port Mode Type Size Description SW[16:14] (^) Input STD_LOGIC_VECTOR (^) 3-bits Register 1 read address SW[13:11] (^) Input STD_LOGIC_VECTOR (^) 3-bits Register 2 read addresses SW[10:8] (^) Input STD_LOGIC_VECTOR (^) 3-bits Register write addresses SW[7:0] (^) Input STD_LOGIC_VECTOR (^) 8-bits Register write data KEY[3] (^) Input STD_LOGIC_VECTOR (^) 1-bit Write enable for the bypassed ARF. KEY[2] (^) Input STD_LOGIC_VECTOR (^) 1-bit Synchronous reset. Rests all registers to 0x0. CLOCK_27 (^) Input STD_LOGIC (^) 1-bits The 27MHz DE2 on-board clock oscillator HEX3[6:0] (^) Output STD_LOGIC_VECTOR (^) 7-bits The most-significant hex 7-segment display HEX2[6:0] (^) Output STD_LOGIC_VECTOR (^) 7-bits The next low-order hex 7-segment display HEX1[6:0] (^) Output STD_LOGIC_VECTOR (^) 7-bits The next low-order hex 7-segment display HEX0[6:0] (^) Output STD_LOGIC_VECTOR (^) 7-bits The least-significant hex 7-segment display

Table 6: Interface Specification of the 8 x 8-bit Bypassed ARF DE2 FPGA System

You must perform the following:

  • Utilize one VHDL PROCESS statement along with IF-ELSE constructs to implement the I/O registers.
  • Utilize the following VHDL constructs to implement the 8 x 8-bit bypassed ARF module: o A type called RegisterArray which creates the array of registers. o A VHDL PROCESS and IF-ELSE constructs to implement the write-logic of the ARF. o Utilize the NUMERIC_STD package in the IEEE library for the necessary arithmetic, logical, comparison, shift, rotate, resize, type-conversion, and type-casting operations to implement the read and write logic.
  • Instantiate four hex-to-7 segment display units to interface the bypassed ARF to the 7-segment displays.
  • Use VHDL aliases to alias all of the ARFs I/O ports to provide more meaningful, code-friendly names.

Name the top-level design file arf_8by8bit.vhd.

(b) Follow the directions below to program the Cyclone II FPGA with the 8 x 8-bit pMIPS bypassed ARF DE2 system.

  1. Assign the Altera Cyclone II EP2C35F672C6 as the target device. a. Navigate to Assignments > Device… b. For the Family drop-down menu, choose Cyclone II. c. In the Available Items Menu, select the EP2C35F672C6 device and click the OK button.
  2. Assign the appropriate FPGA pins by importing the DE2_pin_assignments.csv file. a. Navigate to Assignments > Import Assignments… b. Browse to find the DE2_pin_assignments.csv file for importing pin assignments. c. Click the OK button.
  3. Prepare for a full compilation by first performing any synthesis optimizations (via the GUI or VHDL attributes) you believe will allow for as optimal of a circuit realization as possible. Additionally, apply the smallest timing constraints for fMAX, tSU, tH, tCO, and tPD using the Classic Timing Analyzer Tool to obtain the best possible timing for the system. You may need to iterate through applying synthesis optimizations and timing constraints multiple times to before obtaining the best results. Do not move on to the next step until this step is complete.
  4. Perform a full compilation by using the Start Compilation toolbar button.
  5. Perform a timing simulation and verify the correctness of the 8 x 8-bit pMIPS bypassed ARF DE2 system.
  6. Program the DE2 FPGA Board using the Programmer Tool.