ECE 2030 Computer Engineering Fall 2099
4 problems, 5 pages Exam Three 17 November 2099
1
Name (print) _____________________________________________________
1234 total
25 30 20 25 100
This exam is certified Y2K compliant.
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Guidelines and tips
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Latch and Mux - Computer Engineering - Exam, Exams of Computer Science
Main points of this past exam are: Latch and Mux, Counting Your Blessings, Transparent Latches, DesignToggle, Clock Inputs, Toggle Enable, Clear Signal, LabelSignals, Enable Inputs, Assume Clock Inputs
Typology: Exams
2012/2013
1 / 5
This page cannot be seen from the preview
Don't miss anything!
Related documents
Partial preview of the text
Download Latch and Mux - Computer Engineering - Exam and more Exams Computer Science in PDF only on Docsity!
4 problems, 5 pages Exam Three 17 November 2099
Name (print) _____________________________________________________
1 2 3 4 total
This exam is certified Y2K compliant.
4 problems, 5 pages Exam Three 17 November 2099
Problem 1 (2 parts, 25 points) Counting Your Blessings
Part A (12 points) Design a toggle cell using only transparent latches, a 4-to-1 mux, and an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output Out. Label all signals. The clear signal should take precedence over the toggle enable.
I (^0) I (^1) I (^2) I (^3) S 1 S 0
Out
latch
En
In Out
latch
En
In Out
Part B (13 points) Now combine three of these toggle cells to build a divide by five counter. Your counter should have active high external clear and external count enable inputs, a max count and three count outputs O 2 , O 1 , O 0. Be sure your design can be cascaded. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected.
4 problems, 5 pages Exam Three 17 November 2099
Problem 3 (2 parts, 20 points) State Machine
Part A (15 points) Using the following state table, complete the state diagram below. Use correct state diagram notation. S variables are the current state. NS variables are the new state. X and Y are inputs while A is an output.
S 1 S 0 Y X NS 1 NS 0 A S 1 S 0 Y X NS 1 NS 0 A 0 0 X 0 0 0 0 1 0 X 0 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 X 0 0 1 0 1 1 X 0 1 1 0 0 1 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1
Part B (5 points) Suppose the primary output of this state machine is S 1 and S 0. Briefly describe what this state machine does.
4 problems, 5 pages Exam Three 17 November 2099
Problem 4 (2 parts, 25 points) A Logic Approach
Part A (10 points) Using only pass gates and inverters, design a four to one multiplexer. Label the inputs I 0 , I 1 , I 2 , I 3 , S 1 , and S 0. Label the output Out. For a clearer picture, only attach the control signal for the active high control input of the pass gates.
Part B (15 points) Assuming X controls S0 and Y controls S1, determine the multiplexer input values (LF 3 -LF 0 ) needed to produce the listed logical functions.
Y X out 0 0 LF 0 0 1 LF 1 1 0 LF 2 1 1 LF 3
logical function LF 3 LF 2 LF 1 LF 0