Laboratory Two
Layout Editing and Performance Analysis
References
Mentor On-Line Help Manual
Mentor Tutorials posted on the ECE 4500/5950 Class Web Page
Objectives
1. Understand the fabrication processes for NMOS and PMOS transistors.
2. Learn the use of the schematic editor Design Architect.
3. Evaluate the performance of the circuit using Eldo and Xelga
4. Learn the layout editing commands in IcStation.
5. Perform parasitic extraction using Calibre xRC
Tasks
1. Capture the schematic diagram of a logic gate given in Figure 1 using Design Architect. The
minimum feature sizes for L and W are 1.2µm and 2.0µm, respectively.
Name your file like xxx_lab2.
2. Design a suitable functional simulation for the circuit using Eldo and Xelga.
Give the logic function for the circuit on the basis of your simulation results.
3. Use Eldo and Xelga for DC sweep and transient analysis.
From DC sweep, find NM and NM
HL
. From transient analysis, calculate
tPHL, tPLH, and tP.
4. Create a layout for the circuit.
5. Perform parasitic extraction.
Lab Report (hard copy) should include:
a) Discussion of your design (a transistor-level schematic diagram is included).
b) Printout of the schematic diagram.
c) Printout of the layout.
d) Printouts of the functional simulation using Eldo and Xelga.
e) Printouts of the transient simulations.
f) Final specs of your circuit (logic levels VOL, and VOL, delay times tPLH and tPHL, the average
delay tP, and the size of the actual layout area).