Lecture notes of ACA, Lecture notes of Advanced Computer Architecture

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Advance

Computer

Architecture

Dr. Haroon Mahmood

Assistant Professor

NUCES Lahore

2 Advance Computer Architecture

What is Computer

Architecture?

Computer Architecture =

Instruction Set

Architecture +

Machine Organization (e.g.,

Pipelining, Memory

Hierarchy, Storage

systems, etc) +

Hardware implementation

4 Advance Computer Architecture

Instruction Set

Architecture (ISA)3.^ Addressing Modes

 (^) Register  (^) Immediate  (^) Displacement

4. Types and size of Operads

 (^) 8 bit, 16 bit …

5. Operations

 (^) Data transfer  (^) Arithmetic logical  (^) Control  (^) Floating point

5 Advance Computer Architecture

Instruction Set

Architecture (ISA)6.^ Control flow instructions

 (^) Conditional branches, unconditional jumps, Procedure calls  (^) MIPS test contents of registers for conditional branches  (^) 80x86 and ARM test condition code bits

7. Encoding an ISA

 (^) Fixed length (simplifies instruction decoding)  (^) Variable length (less space)

7 Advance Computer Architecture

Clock

 Synchronizes Processor and Bus operations

 Clock cycle = Clock period = 1 / Clock rate

 Clock rate = Clock frequency = Cycles per

second

 (^) 1 Hz = 1 cycle/sec 1 KHz = 10^3 cycles/sec  (^) 1 MHz = 10^6 cycles/sec 1 GHz = 10^9 cycles/sec  (^) 2 GHz clock has a cycle time = 1/(2×10^9 ) = 0.5 nanosecond (ns) Cycle 1 Cycle 2 Cycle 3

8 Advance Computer Architecture

Registers

 (^) Registers are high speed memory inside the CPU  (^) Eight 32-bit general-purpose registers  (^) Six 16-bit segment registers  (^) Processor Status Flags (EFLAGS) and Instruction Pointer (EIP) CS SS DS ES EIP EFLAGS 16-bit Segment Registers EAX EBX ECX EDX 32-bit General-Purpose Registers FS GS EBP ESP ESI EDI

10 Advance Computer Architecture

Accessing parts of

registers

 (^) EAX, EBX, ECX, and EDX are 32-bit Extended registers  (^) Programmers can access their 16-bit and 8-bit parts  (^) Lower 16-bit of EAX is named AX  (^) AX is further divided into  (^) AL = lower 8 bits  (^) AH = upper 8 bits  (^) ESI, EDI, EBP, ESP have only 16-bit names for lower half

11 Advance Computer Architecture

EFlags register

 (^) Status Flags  (^) Status of arithmetic and logical operations  (^) Control and System flags  (^) Control the CPU operation  (^) Programs can set and clear individual bits in the EFLAGS register

13 Advance Computer Architecture

Instruction Execution Cycle

I2 I3 I PC (^) program I instruction register op op memory fetch ALU registers write decode execute read write (output) registers flags I...

14 Advance Computer Architecture

MIPS Introduction

 Data types:

 (^) Instructions are all 32 bits  (^) byte(8 bits), halfword (2 bytes), word ( bytes)  (^) a character requires 1 byte of storage  (^) an integer requires 1 word (4 bytes) of storage

 Registers

 (^) 32 general purpose registers  (^) register preceded by $ in assembly language instruction  (^) two formats for addressing:  (^) using register number e.g. $0 through $

16 Advance Computer Architecture

1st and 2nd Instruction

cycles

 Instruction fetch (IF)

IR Mem[PC];

NPC PC + 4

 Instruction decode & register fetch (ID)

A Regs[IR

6..

];

B Regs[IR

11..

];

Imm ((IR

16

16

# # IR

16..

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3rd Instruction cycle

 Execution & effective address (EX)

 (^) Memory reference  (^) ALUOutput A + Imm  (^) Register - Register ALU instruction  (^) ALUOutput A func B  (^) Register - Immediate ALU instruction  (^) ALUOutput A op Imm  (^) Branch  (^) ALUOutput NPC + Imm; Cond (A op

19 Advance Computer Architecture

5th Instruction cycle

 Write-back (WB)

 (^) Register - register ALU instruction  (^) Regs[IR 16..20]^ ALUOutput  (^) Register - immediate ALU instruction  (^) Regs[IR 11..15]^ ALUOutput  (^) Load instruction  Regs[IR11..15] LMD