ECE 511: Computer Architecture 4 Oct 2004
Lecture 11: Loose Ends
Lecturer: Matt Frank Scribe: Troy Becicka
1 How does the scoreboard determine when the source registers
for an instruction are ready?
Consider the following set of instructions in the scoreboard:
Instruction True dep. Issue Ready (complete)
MUL10 R5āR1, R20 0 10
ADD5R6āR3, R40 1 6
SUB5R7āR5, R610 10 15
ADD5R12 āR8, R90 2 7
ADD5R13 āR10, R11 0 3 8
DIV20 R14 āR12, R13 8 8 28
The scoreboard maintains a Register Ready Table, which has one bit for each physical register.
As an instruction enters the scoreboard (dispatch), its physical destination register is marked not
ready. As an instruction completes, its physical destination register is marked ready.
There is a lot of pressure on the Register Ready Table. For instance, with a scoreboard size of
8, we need 2 write ports and 16 read ports. We need two write ports because we must mark the
entering (dispatched) instructionās destination register not ready and the completing instructionās
destination register ready. We need 16 read ports because all 8 instructions in the scoreboard need
to read the ready status of both of their source registers each cycle.
Assume we have 27= 128 physical registers. In order to allow each scoreboard instruction to
access the Register Ready Table (RRT), we could route all 128 RRT output lines to the two source
register columns of the scoreboard. Each physical source register Riwould then use the 7-bit i
value as a MUX select to select the correct ready bit. Each instruction in the scoreboard could then
AND its two ready bits together to determine if the instruction was ready to issue.
An alternative is to have each instruction in the scoreboard watch the writeback bus and com-
pare each of its source registers with the name of the physical destination register being written
back. However, we would still need the RRT since an instructionās source registers may have be-
come ready well before the instruction entered the scoreboard.
When multiple instructions are ready to issue on the same cycle, we can use a priority encoder
to select which instruction to issue first.
If you have a bypass path from the end of the Execute stage to the beginning of Execute, you
need to let the scoreboard RRT know that the register whose value you are bypassing will be ready
before it is written to the register file.
11: Loose Ends-1
