LOGIC CIRCUITS, exam paper, UPTU, Exams of Analysis and Design of Digital Integrated Circuits

Karnaugh map, BCD, CMOS, nand, nor, flip flop

Typology: Exams

2010/2011

Uploaded on 08/29/2011

nihira
nihira 🇮🇳

4.3

(63)

90 documents

1 / 3

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
pf3

Partial preview of the text

Download LOGIC CIRCUITS, exam paper, UPTU and more Exams Analysis and Design of Digital Integrated Circuits in PDF only on Docsity!

AQT ATO Printed Pages : 3 BME - 403 (Following Paper ID and Roll No. to be filled in your Answer Book) POEM Rolo TT TTT B. Tech. (SEM. TV) EXAMINATION, 2006-07 LOGIC CIRCUITS Time : 3 Hours} {Total Marks : 100 Note : (1) Answer all questions. (2) All questions carry equal marks. 1 Attempt any two parts of the following : 10x2=20 (a) Minimize the following function by Tabular method. f (w, x, y, 2) = 5 (0,1,4,5,6,7,9,10,11,14,15) (b) @ Perform the following subtraction using q’s complement method. 0011-1001 - 0001-1110 qi) Explain with example how don’t care conditions are implemented in K-map minimization. (c) Design a combinational circuit that compares two 4-bit number A and B to check if they are equal or not. 2 Attempt any two parts of the following : 10x2=20 a) What are synchronous and asynchronous se- y y quential circuits? Write the procedure for the analysis of a sequential circuit. V-3078] 1 [Contd...