Memory Management in Computer Systems Programming - Lecture Slides | CS 201, Study notes of Computer Science

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Memory Management

Gerson Robboy

Portland State University

Topics Topics

 P6 address translation

 Linux memory management

 Linux page fault handling

 memory mapping

class20.ppt

Building the Address Space

Source

code

• Load time:

• Allocate primary memory

• Adjust addresses in address space

• Copy address space from secondary to primary memory

Loader Process

address

space

Primary

memory

C

Reloc

Object

code

Link

Edit

Library

code

Other

objects

Secondary

memory

With multiple processes

Operating

System

Process 3

Process 0

Process 2

Process 1

Unused

In Use

Issue: Where do you load

p

i

’s address space into

primary memory?

p

i

Dynamic Memory Allocation

Process wants to change the size of its address Process wants to change the size of its address

space space

 Malloc/sbrk

 Stack growth – temporary variables

May have to dynamically relocate the program May have to dynamically relocate the program

Some problems with physical memory only

 With multi-tasking, you have to dynamically relocate

programs when loading them.

 If the stack overflows the area allocated for it, we ’ re in

trouble.

 The same with the heap.

 With swapping, you have to dynamically relocate programs

each time they are swapped in.

 Is that even possible? How would you handle locally declared

pointers?

VM Address Translation

Processor

On-chip

MMU

Main

a Memory

a'

virtual address physical address

Example

32 bit addresses, page size is 4096 = 0x1000 32 bit addresses, page size is 4096 = 0x

How many bits is the offset into a page? How many bits is the offset into a page?

A page-aligned address has how many low order zero A page-aligned address has how many low order zero

bits? bits?

Example

32 bit addresses, page size is 4096 = 0x1000 32 bit addresses, page size is 4096 = 0x

Consider some address: 0x3e80a123 Consider some address: 0x3e80a

Low order 12 bits: offset within the page: 0x123 Low order 12 bits: offset within the page: 0x

Address with low order 12 bits masked out: address of Address with low order 12 bits masked out: address of

the page: 0x3e80a000 the page: 0x3e80a

High order 20 bits alone are the page number: 0x3e80a High order 20 bits alone are the page number: 0x3e80a

Clarification

Page tables and page directories are data structures in Page tables and page directories are data structures in

memory. memory.

The O. S. kernel (software) sets them up and manages The O. S. kernel (software) sets them up and manages

them. them.

The format of the contents is defined by hardware. The format of the contents is defined by hardware.

The hardware uses them on every memory reference, to The hardware uses them on every memory reference, to

convert a virtual address to a physical address. convert a virtual address to a physical address.

The PDBR tells the hardware where to look. The PDBR tells the hardware where to look.

Implications for memory management

To allocate memory for a process, now the O. S. To allocate memory for a process, now the O. S.

doesn doesn ’’ t have to manage contiguous blocks oft have to manage contiguous blocks of

memory. memory.

All it has to do is find a set of available pages All it has to do is find a set of available pages

 The pages can be scattered all over the place

 The pages are mapped into contiguous virtual memory

regions.

 No more fragmentation

Analogous to allocating files on a disk Analogous to allocating files on a disk – – fixed sizefixed size

blocks. blocks.

How ia32 Maps Virtual

Addresses to Physical Ones

PDE

PDBR

physical address of page table base (if P=1) physical address of page base (if P=1) physical address of page directory word offset into page directory word offset into page table

page directory page table

VPN

VPO

VPN2 Virtual address

PTE

PPN PPO

Physical address

word offset into physical and virtual page

Exercise

Suppose a computer has 16-bit virtual addresses, 16-bit Suppose a computer has 16-bit virtual addresses, 16-bit

physical addresses, a page size of 64 bytes, and two- physical addresses, a page size of 64 bytes, and two-

level page tables, like a pentium. level page tables, like a pentium.

 How many bits is the VPO?

 How many entries in a page table?

 How many bits is VPN0?

 How many bits is VPN1?

Some Arithmetic

VPO of 12 bits VPO of 12 bits  A page is 4096 bytesA page is 4096 bytes

Each PD and PT occupies one page. Each PD and PT occupies one page.

Each PDE and PTE is 32 bits (4 bytes) Each PDE and PTE is 32 bits (4 bytes) 

 Each page directory contains 1024 PDEs

 Each page table contains 1024 PTEs

 Each page table points to 1024 pages

1024 pages * 4Kbytes = 4 MB covered by a page table 1024 pages * 4Kbytes = 4 MB covered by a page table

4MB * 1024 PDEs = 4 GB memory space covered by a 4MB * 1024 PDEs = 4 GB memory space covered by a

page directory. page directory.

ia32 Page Table Structure

Page directory Page directory

 1024 4-byte page directory

entries (PDEs) that point to page

tables

 one page directory per process.

 page directory must be in

memory when its process is

running

 always pointed to by PDBR

Page tables: Page tables:

 1024 4-byte page table entries

(PTEs) that point to pages.

 page tables can be paged in and

out.

page

directory

Up to

page

tables

PTEs

PTEs

PTEs

PDEs