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Memory Management - Operating Systems - Lecture Notes | COP 4600, Study notes of Operating Systems

University of Central Florida (UCF)Operating Systems

Memory Management (part2) Material Type: Notes; Class: Operating Systems; Subject: Computer Programming; University: University of Central Florida; Term: Summer Session 2011;

Typology: Study notes

2010/2011

Uploaded on 07/14/2011

jww1990
jww1990 🇺🇸

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COP 4600: Intro To OS (Memory Management –Part 2) Page 1 © Dr. Mark Llewellyn
COP 4600 –Summer 2011
Introduction To Operating Systems
Memory Management –Part 2
Department of Electrical Engineering and Computer Science
Computer Science Division
University of Central Florida
Instructor : Dr. Mark Llewellyn
[email protected]
HEC 236, 407-823-2790
http://www.cs.ucf.edu/courses/cop4600/sum2011
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Download Memory Management - Operating Systems - Lecture Notes | COP 4600 and more Study notes Operating Systems in PDF only on Docsity!

COP 4600 – Summer 2011

Introduction To Operating Systems

Memory Management – Part 2

Department of Electrical Engineering and Computer Science

Computer Science Division

University of Central Florida

Instructor : Dr. Mark Llewellyn

[email protected]

HEC 236, 407-823-

http://www.cs.ucf.edu/courses/cop4600/sum

Memory Management

Memory Management Methods

Contiguous Allocation Non-Contiguous Allocation

Single Partition Multiple Partition

Fixed

Allocation

Dynamic

Allocation

Segmentation Paging

"Basic"

Paging

Demand

Paging

(Virtual Memory)

Assignment of Process Pages to Free Frames

Assignment of Process Pages to Free Frames

Paging (cont.)

• When presented with a logical address (page number,

offset), the processor uses the page table to produce a

physical address (page frame, offset).

• The next page, illustrates the page tables for the processes

in the previous example at the time illustrated by figure

(f), which is shown again for continuity.

Page Tables for Example on Page 4

Process B currently has no pages loaded in main memory

Paging – Address Translation Scheme

• Address generated by CPU is divided into:

– Page number ( p ) – used as an index into a page table which

contains base address of each page in physical memory.

– Page offset (d) – combined with base address to define the

physical memory address that is sent to the memory unit

– For given logical address space 2 m^ and page size 2 n

page number page offset
p d
m - n n

Paging Hardware

Simple Paging Example

32-byte memory
and 4-byte pages

Frame Numbers

Free Frames

Before allocation After allocation

Associative Memory

• Associative memory – parallel search

Address translation (p, d)

– If p is in associative register, get frame # out

– Otherwise get frame # from page table in memory

Page # Frame #

Paging Hardware With TLB

Memory Protection

• Memory protection implemented by associating a protection bit

with each frame.

• Valid-invalid bit attached to each entry in the page table:

– “valid” indicates that the associated page is in the process’

logical address space, and is thus a legal page

– “invalid” indicates that the page is not in the process’ logical

address space

Valid (v) or Invalid (i) Bit In A Page Table