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Virtual Memory
2
Memory Management Unit
(or TLB)
The position and function of the MMU
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- Virtual Memory
- Divided into equal- sized pages
- A mapping is a translation between - A page and a frame - A page and null
- Mappings defined at runtime - They can change
- Address space can have holes
- Process does not have to be contiguous in physical memory - Physical Memory - Divided into equal-sized frames
Virtual Address Space
Physical Address Space
Paging
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Typical Address
Space Layout
- Stack region is at top, and can grow down
- Heap has free space to grow up
- Text is typically read-only
- Kernel is in a reserved, protected, shared region
- 0-th page typically not used, why?
Virtual Address Space
Kernel
Stack
Shared Libraries
BSS (heap)
Data
Text (Code)
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be only partially
resident
- Allows OS to store individual pages on disk
- Saves memory for infrequently used data & code
- What happens if
we access non-
resident
memory?
Virtual Address Space
Physical Address Space
Disk
Programmer’s perspective : logically present System’s perspective : Not mapped, data on disk
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Proc 1 Address Space
Physical Address Space
Proc 2 Address Space
Disk
Currently running
Memory Access
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Page Faults
- Referencing an invalid page triggers a page fault
- An exception handled by the OS
- Broadly, two standard page fault types
- Illegal Address (protection error)
- Signal or kill the process
- Page not resident
- Get an empty frame
- Load page from disk
- Update page (translation) table (enter frame #, set valid bit, etc.)
- Restart the faulting instruction
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resident part of
address space
Virtual Address Space
Physical Address Space
Page Table
• Note: Some implementations store disk
block numbers of non-resident pages in
the page table (with valid bit Unset )
9 10
Shared Pages
- Private code and data
- Each process has own copy of code and data
- Code and data can appear anywhere in the address space - Shared code - Single copy of code shared between all processes executing it - Code must not be self modifying - Code must appear at same address in all processes
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Proc 1 Address Space
Physical Address Space
Page Table
Proc 2 Address Space
Page Table
Two (or more) processes running the same program and sharing the text section
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Page Table Structure
• Page table is (logically) an array of
frame numbers
• Each page-table entry (PTE) also has
other bits
Page Table
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Page Tables
- Page tables are implemented as data structures in main memory
- Most processes do not use the full 4GB address space
- e.g., 0.1 – 1 MB text, 0.1 – 10 MB data, 0.1 MB stack
- We need a compact representation that does not waste space - But is still very fast to search
- Three basic schemes
- Use data structures that adapt to sparsity
- Use data structures which only represent resident pages
- Use VM techniques for page tables (details left to extended OS)
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Two-level Page
Table
- 2 nd^ –level page tables representing unmapped pages are not allocated - Null in the top-level page table
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Two-level Translation Example Translations
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Alternative: Inverted Page Table
PID VPN next
PID VPN offset
Index 0 1 2 3 4 5 6 …
IPT: entry for each physical frame
Hash Anchor Table (HAT)
Hash
ctrl
Alternative: Inverted Page Table
PID VPN next
PID VPN offset
Index 0 1 2 … 0x40C 0x40D … …
Hash Anchor Table (HAT)
Hash
ctrl
0x5 0x
1 0x1A 0x40C
0 0x5 0x
2
0x40C 0x
ppn offset
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Inverted Page Table (IPT)
- “Inverted page table” is an array of page
numbers sorted (indexed) by frame number (it’s
a frame table).
- Algorithm
- Compute hash of page number
- Extract index from hash table
- Use this to index into inverted page table
- Match the PID and page number in the IPT entry
- If match, use the index value as frame # for translation
- If no match, get next candidate IPT entry from chain field
- If NULL chain entry ⇒ page fault 26
Properties of IPTs
- IPT grows with size of RAM, NOT virtual address space
- Frame table is needed anyway (for page replacement, more later)
- Need a separate data structure for non-resident pages
- Saves a vast amount of space (especially on 64-bit systems)
- Used in some IBM and HP workstations
Given n processes
• how many page tables will the system
have for
- ‘normal’ page tables
- inverted page tables?
Another look at sharing…
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Proc 1 Address Space
Physical Address Space
Page Table
Proc 2 Address Space
Page Table
Two (or more) processes running the same program and sharing the text section
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- Problem:
- Each virtual memory reference can cause two physical memory accesses - One to fetch the page table entry - One to fetch/store the data ⇒Intolerable performance impact!!
- Solution:
- High-speed cache for page table entries (PTEs)
- Called a translation look-aside buffer (TLB)
- Contains recently used page table entries
- Associative, high-speed memory, similar to cache memory
- May be under OS control (unlike memory cache)
VM Implementation Issue
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Recap - Simplified Components of
VM System
CPU
Frame Pool
1 3 2
TLB
Virtual Address Spaces (3 processes)
Page Tables for 3 processes (^) Frame Table
Physical Memory 38
Recap - Simplified Components of
VM System
CPU
Frame Pool
TLB
Virtual Address Spaces (3 processes) (^) Inverted Page Table
Physical Memory
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MIPS R3000 TLB
- N = Not cacheable
- D = Dirty = Write protect
- G = Global (ignore ASID in lookup) - V = valid bit - 64 TLB entries - Accessed via software through Cooprocessor 0 registers - EntryHi and EntryLo 40
R3000 Address
Space Layout
- kuseg:
- 2 gigabytes
- TLB translated (mapped)
- Cacheable (depending on ‘N’ bit)
- user-mode and kernel mode accessible
- Page size is 4K
kseg
kuseg
0x
0x
kseg
kseg
0xA
0xC
0xFFFFFFFF
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R3000 Address
Space Layout
- Switching processes switches the translation (page table) for kuseg kseg
Proc 3 kuseg
0x
0x
kseg
kseg
0xA
0xC
0xFFFFFFFF
Proc 2 kuseg
Proc 1 kuseg
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R3000 Address
Space Layout
- kseg0:
- 512 megabytes
- Fixed translation window to physical memory - 0x80000000 - 0x9fffffff virtual = 0x00000000 - 0x1fffffff physical - TLB not used
- Cacheable
- Only kernel-mode accessible
- Usually where the kernel code is placed
kseg
kuseg
0x
0x
kseg
kseg
0xA
0xC
0xffffffff
Physical Memory
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R3000 Address
Space Layout
- kseg1:
- 512 megabytes
- Fixed translation window to physical memory - 0xa0000000 - 0xbfffffff virtual = 0x00000000 - 0x1fffffff physical - TLB not used
- NOT cacheable
- Only kernel-mode accessible
- Where devices are accessed (and boot ROM)
kseg
kuseg
0x
0x
kseg
kseg
0xA
0xC
0xffffffff
Physical Memory 44
R3000 Address
Space Layout
- kseg2:
- 1024 megabytes
- TLB translated (mapped)
- Cacheable
- Only kernel-mode accessible
- Can be used to store the virtual linear array page table
kseg
kuseg
0x
0x
kseg
kseg
0xA
0xC
0xffffffff
