Download Memory: Memory Cells - Lecture Notes | ECEN 5263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity!
Memory
Fig. 11.2, p. 715 General organization of memory. There are n address inputs and 2m^ data inputs/outputs. One can have any number of data lines desired; it does not have to be a
power of 2. The row decoder selects one of the 2n-k^ rows which all drive data onto each of
the 2m+k^ columns. The column decoder selects 1 out of every 2k^ columns to give the 2m data inputs/outputs. This two-dimensional addressing scheme allows smaller decoders to be used and allows the circuit designer to layout the memory cells in a convenient size array instead of having the same number of columns as data lines.
Dynamic and static RAM as well as ROM are all based on this same design. Differences in the memory cells produce the different kinds of memory.
Memory Cells
Dynamic RAM (DRAM). Dynamic RAM is the most dense memory because it uses the minimum possible number of circuit components. It relies on storing a charge on a float- ing node (internal capacitor) which can be can be connected (a pass transistor) to the col- umn sense amplifiers. The implementation of a single memory cell is shown in
Fig. 11.26a, p. 734
The charge is stored on the parasitic capacitance, Ccell, at the unconnected end of the tran-
sistor. The bit line capacitance, Cbit, is usually much larger than the cell capacitance since
the source drain capacitance of every memory cell connected to the bit line contributes to the bit line capacitance.
Since Ccell << Cbit, only a small change in voltage occurs on the bit line when the transis-
tor is turned on to read the stored voltage. This small change can be found from charge sharing between the bit line and the storage node. We assume that the bit line is initially at Vbit(0) before the transistor turns on and that
V (^) cell ( ) 0
0 , logic 0
^ V^ dd^ –^ V^ T,logic 1
The sum of the charges on the memory cell storage node and the bit line is
Q =C (^) cell V (^) cell ( ) 0 +C (^) bit V (^) bit ( ) 0
which must be preserved after the pass transistor turns on. After the transistor turns on, the bit line and storage node will eventually reach the same final voltage, Vf. The bit line
capacitance and the storage node capacitance are now in parallel so that
Q = ( C (^) cell +C (^) bit)V (^) f.
Since the total charge must be the same before and after the transistor switches on,
( C (^) cell +C (^) bit)V (^) f = C (^) cell V (^) cell ( ) 0 +C (^) bit V (^) bit ( ) 0
V (^) f
C (^) cell C (^) cell +C (^) bit
---------------------------V (^) cell ( ) 0
C (^) bit C (^) cell +C (^) bit
= +---------------------------V (^) bit ( ) 0
which is exactly the same capacitor divider result as for charge sharing, but this time the charge is shared intentionally. The change on the bit line voltage is ∆V = V (^) f – V (^) bit ( ) 0 C (^) cell C (^) cell +C (^) bit
= ---------------------------^ (V (^) cell ( ) 0 – V (^) bit ( ) 0 )
If V (^) bit ( ) 0 = (V (^) dd – V (^) T) ⁄ 2 , then ∆V for a stored 1 is the same magnitude as ∆V for a
stored 0, but in the opposite direction
∆V
C (^) cell C (^) cell +C (^) bit
( V (^) dd – V (^) T) 2
as shown in
Fig. 11.26b, p. 734
Since Ccell << Cbit, the final voltage is almost the same as the initial bit line voltage and
∆V is very small. This small voltage change can be very difficult to distinguish from
noise on the bit line. The choice of V (^) bit ( ) 0 = ( V (^) dd – V (^) T) ⁄ 2 gives equal noise margins
for reading a logic 0 and logic 1.
The voltage change on the bit line is larger if Ccell is made as large as possible. If Ccell is
fabricated as a parasitic capacitance, then
C (^) cell C A
= ----^ WL
and we want to choose a layer with the largest (C/A) to minimize the area taken up by the storage capacitance. The MOSFET gate capacitor provides the largest (C/A) in most fab- rication processes. A permanently turned on FET with a large gate area is often used as the storage capacitance.
time, only one of the inputs of a sense amp changes by ∆V while the other remains unchanged at Vbit(0). The sense amp rejects noise common to both input lines by amplify-
ing the difference between the bit line voltages from different sub-arrays. Unfortunately, the noise in each sub-array can be quite different so that this noise canceling scheme is not effective for the large memory arrays commonly encountered in modern DRAM memory chips.
A better scheme is the folded bit lines in fig. 11.30, p. 737, which cancels noise from adja- cent bit lines where the noise is more likely to be the same. Note that the memory cell array appears to have significant wasted space compared to the previous approach. Fortu- nately, a very area efficient layout is possible, fig. 11.31, p. 737.
Refresh
The charge on the storage capacitor is drained away by leakage currents in the transistor, just as in dynamic logic gates, in times of the order of 1 msec (or much less in deep submi- cron processes). Thus, every dynamic RAM cell must be read and written back (refreshed) at least 1000 times per second. To keep the time taken up by the refresh cycles to a minimum, all of the cells in the same row can be refreshed at the same time. This is possible since each column in the memory array has its own sense amp. For example, in
fig. 11.2, p. 715, there are 2m+k^ sense amps even though there are only 2m^ I/O bits. Instead of using the column decoder, the data from all of the column sense amps can be written back at once to the selected row during the refresh cycle.
Static RAM (SRAM). Static RAM is the fastest writable memory (ROMs are faster), but static RAM takes more transistors than dynamic RAM and is therefore more costly per bit stored. Static RAM does not rely on charge storage, but on cross coupled inverters to maintain the stored logic value. No refresh is necessary.
Fig. 11.4, p. 716 CMOS static RAM. Note: no DC power consumption.
The word line turns the nMOS pass transistors on or off which connects the cross coupled inverters to the bit and bit_b lines (data lines) which allows reading or writing the data on the bit lines out of or into the memory cell. The nMOS pass transistors make the memory cell look like non-full swing logic which would seem to imply that there is DC power con- sumption. However, the internal nodes of the memory cell are full swing, because the cross coupled inverters drive these nodes all the way high or low.
Instead of nMOS pass transistors connecting to the bit lines, full CMOS transmission gates could be used (fig. 11.3a, p. 716). Adding the pMOS transistors to make the trans- mission gate takes up more area which is very bad since the additional area gets multiplied by the number of memory cells in the memory. Since the memory cell can be made to work with only nMOS pass transistors, it is usually done that way.
Stick diagram fig. 11.5, p. Layout fig. 11.6, p. 717 and inside front cover
Transistor Model for Memory Cell Analysis
The correct operation of the SRAM memory cells depends on the current-voltage relation- ships of the transistors. If we use the drain current equations developed earlier, the result- ing equations are difficult to solve. On the other hand, the simple channel resistance model is too inaccurate to correctly predict the behavior of the SRAM memory cells. The following piece-wise linear model is a good compromise.
I (^) Dn
a (^) n GV (^) DS
G V(^ GS^ – V^ Tn)
V (^) GS <V (^) Tn V (^) GS > V (^) Tn,V (^) DS <V (^) DSsatn V (^) GS > V (^) Tn,V (^) DS >V (^) DSsatn
where
V (^) DSsatn
V (^) GS – V (^) Tn a (^) n
=^ ------------------------
and
I (^) Dp
a (^) p GV (^) DS
G V(^ GS – V^ Tp)
V (^) GS >V (^) Tp V (^) GS < V (^) Tp,V (^) DS >V (^) DSsatp V (^) GS < V (^) Tp,V (^) DS <V (^) DSsatp
where
V (^) DSsatp
V (^) GS – V (^) Tp a (^) p
=^ ------------------------
All parameters except VTp are positive, and VTp is negative. Reasonable values for a are
usually slightly greater than one. The parameters an, ap, VTn and VTp are process constants
whereas the conductance parameter,
G
R
-------W
L
=^ -----
is determined by the transistor size and can be different for each transistor.
A useful property of this model is that it allows a solution for Vinv, the switching voltage of
the inverter which is important for understanding the memory cell.
Vinv Vinv
I (^) Dn = G (^) n ( V (^) GSn – V (^) Tn) = G (^) n ( V (^) inv – V (^) Tn) I (^) Dp = G (^) p ( V (^) GSp – V (^) Tp) = G (^) p (V (^) inv – V (^) dd–V (^) Tp) I (^) Dn = –I (^) Dp G (^) n ( V (^) inv – V (^) Tn) =–G (^) p ( V (^) inv – V (^) dd–V (^) Tp)
V (^) inv
G (^) n V (^) Tn +G (^) p ( V (^) dd – V (^) Tp) G (^) n +G (^) p
Vdd
bit cell cell bit
G (^) npass (V (^) dd – V (^) cell–V (^) Tn)
a (^) n G (^) ncell
G (^) pcell ( V (^) dd – V (^) cell– V (^) Tp)
a (^) n G (^) npass
G (^) npass ( V (^) dd – V (^) cell–V (^) Tn) =a (^) n G (^) ncell V (^) cell
V (^) cell
G (^) npass G (^) npass +a (^) n G (^) ncell
= ------------------------------------------^ ( V (^) dd – V (^) Tn)
G (^) pcell ( V (^) dd – V (^) cell– V (^) Tp) = a (^) n G (^) npass V (^) cell
V (^) cell
G (^) pcell a (^) n G (^) npass
a (^) n G (^) ncell G (^) npass +a (^) n G (^) ncell
= ------------------------------------------^ ( V (^) dd – V (^) Tn)
G (^) pcell a (^) n G (^) npass
- --------------------- ( V (^) Tn – V (^) Tp)
Since Vcell is the input to the inverter that drives the cell node, the memory will change
states if Vcell > V (^) inv.
G (^) npass G (^) npass +a (^) n G (^) ncell
------------------------------------------ (^) ( V (^) dd – V (^) Tn) > V (^) inv (1)
Since Vcell is the input to the inverter that drives the cell node, the memory will change
states if Vcell < V (^) inv.
G (^) pcell a (^) n G (^) npass
a (^) n G (^) ncell G (^) npass +a (^) n G (^) ncell
------------------------------------------ ( V (^) dd – V (^) Tn) + V (^) Tn – V (^) Tp < V (^) inv (2)
This second inequality is easier to satisfy than the first since nMOS transistors pass a 0 more easily than a 1. This will cause the bottom inverter to switch in our example, which in turn, causes the top inverter to switch rapidly after that. Note that it is not necessary for inequality (1) to be satisfied (overwriting with a 1 bit) as long as inequality (2) is satisfied (overwriting with a 0 bit). This is fortunate since we will not want to satisfy inequality (1) when reading.
Reading from the memory cell
Fig. 11.8, p. 718
Reading is very difficult because the small transistors in the memory cell must drive the large capacitance on the bit lines.
cell cell
Reading 0
bit bit
Example:
The bit line capacitance is dominated by the contribution of the drains of pass transistors from the entire column of memory cells connected to the bit lines. The drain capacitance loads the bit lines even when the pass transistors are turned off. The number of cells in
any single column is equal to the number of rows and we have seen that there are 2n-k rows. Therefore,
Cbit 2 n – k = ( C (^) dpass +C (^) m)
where Cdpass is the drain capacitance per cell of the pass transistor and Cm is the metal
capacitance per cell on the bit line connecting the cells in columns. Because of the multi-
plicative factor of 2n-k, the bit line capacitance is usually much larger than the internal memory cell capacitance.
Cbit »Ccell
Note that inequality (3) is the opposite of inequality (1), i.e. we do not want a 1 on the bit line to overwrite the memory cell.
We do, of course want a 0 on the bit lines to overwrite the cell. In our example of reading a 0 from the bit line, we are also reading a 1 from the bit line. We must be careful to insure the initial voltage on the bit line, Vbit(0), is high enough to not be mistaken for a 0 on the
bit line. This can be done by choosing a Vbit(0) that satisfies inequality (4).
V (^) bit ( ) 0 V (^) dd – V (^) Tn
a (^) p G (^) pcell G (^) npass
–^ --------------------^ (V (^) dd – V (^) inv)
Because of inequality (2) (the need to write 0), the right side is larger than 0. Thus, the bit lines must be initialized (precharged) to some non-zero initial voltage before reading starts. To be absolutely safe, we usually have
V (^) bit ( ) 0 , V (^) bit ( ) 0 ≥V (^) dd – V (^) Tn
so that it will be impossible to overwrite the 0 stored in the memory cell.
Note that the precharge must be done before each read cycle starts or the results of the pre- vious read/write which would still be on the bit line capacitance might overwrite the next memory cell selected for reading. The time to precharge the bit lines is often called the recovery time, and no memory cell can be selected for reading during this time.
bit lines
word select
read delay (^) recover delay
t
t
The top of fig. 11.8, p. 718, has simple bit line precharge circuits. Note that the precharge transistors can be made very wide to give a short recovery delay (precharge time) since the precharge transistors are not duplicated in each memory cell.
Maximum Noise Margin
Inequality (2) is needed for writing and inequality (3) for reading. If we pick values for the transistor parameters that barely satisfy these inequalities, noise could easily cause incorrect operation of the memory. Thus, it is necessary to more than barely satisfy the inequalities by including noise margins.
From inequality (2) for writing
G (^) pcell a (^) n G (^) npass
a (^) n G (^) ncell G (^) npass +a (^) n G (^) ncell
------------------------------------------ (^) ( V (^) dd – V (^) Tn) + V (^) Tn – V (^) Tp =V (^) inv – V (^) NMW
V (^) NMW V (^) inv
G (^) pcell a (^) n G (^) npass
a (^) n G (^) ncell G (^) npass +a (^) n G (^) ncell = – ------------------------------------------^ ( V (^) dd – V (^) Tn) +V (^) Tn – V (^) Tp
From inequality (3) for reading
G (^) npass G (^) npass +a (^) n G (^) ncell
------------------------------------------ (^) ( V (^) dd – V (^) Tn) = V (^) inv – V (^) NMR
V (^) NMR V (^) inv
G (^) npass G (^) npass +a (^) n G (^) ncell = –------------------------------------------^ (V (^) dd – V (^) Tn)
Adequate write noise margin requires the pcell transistor to be smaller than the npass, and adequate read noise margin requires the npass transistor to be smaller than the ncell. Since the noise margins are determined by independent ratios of transistor sizes, there is no rea- son to make one of the noise margins bigger or smaller than the other. The optimum max- imum noise margin is achieved when both noise margins are the same.
V NMR =V NMW
G (^) pcell a (^) n G (^) npass
a (^) n G (^) ncell G (^) npass +a (^) n G (^) ncell
------------------------------------------ (^) ( V (^) dd – V (^) Tn) + V (^) Tn – V (^) Tp
G (^) npass G (^) npass +a (^) n G (^) ncell
= ------------------------------------------^ ( V (^) dd – V (^) Tn)
If we assume that V (^) Tp ≈ V (^) Tn, then most of the terms cancel leaving
G (^) pcell G (^) npass
G (^) npass G (^) ncell
which makes the VNMR and VNMW approximately the same.
Recall that
V (^) inv
G (^) ncell V (^) Tn +G (^) pcell ( V (^) dd – V (^) Tp) G (^) ncell +G (^) pcell
V (^) NM V (^) inv
G (^) npass G (^) npass +a (^) n G (^) ncell
= –------------------------------------------^ ( V (^) dd – V (^) Tn)
Using (5) and again assuming V (^) Tp ≈ V (^) Tngives (after some algebra)
Since the Ccell << Cbit, the cell node changes very quickly to the value calculated previ-
ously in the noise margin analysis
V (^) cell
G (^) npass G (^) npass +a (^) n G (^) ncell
= ------------------------------------------^ ( V (^) dd – V (^) Tn)
and remains there as long as the pass transistor remains in saturation. If Vcell is constant,
so is IDnpass constant and Vbit falls at a constant rate.
d t
dV (^) bit I (^) Dnpass C (^) bit
= –^ -----------------
G (^) npass C (^) bit
--------------- (^) V (^) dd
G (^) npass G (^) npass +a (^) n G (^) ncell
- ------------------------------------------^ ( V (^) dd – V (^) Tn)–V (^) Tn
= – ^
G (^) npass C (^) bit
a (^) n G (^) ncell G (^) npass +a (^) n G (^) ncell
= – ------------------------------------------ (V (^) dd – V (^) Tn)
If the sensitivity of the sense amp is ∆V , then the read access time, tacc, is the time for the
bit line to change by ∆V.
t (^) acc
∆V
dt
dV (^) bit
=^ ---------------
∆V
V (^) dd – V (^) Tn
G (^) npass +a (^) n G (^) ncell G (^) npass ( a (^) n G (^) ncell)
= ------------------------------------------C (^) bit
∆V
V (^) dd – V^ Tn
G (^) npass
a (^) n G^ ncell
+^ --------------------
C
= bit
Putting in explicit width dependence
G (^) ncell = G′n W (^) ncell G (^) npass =G′n W (^) npass
Cbit 2 n – k = ( C′dpassW (^) npass +C (^) m)
gives
t (^) acc^2
n – k ∆V V (^) dd – V (^) Tn
C′dpass a (^) n G′n
W (^) npass W (^) ncell
C′dpass G′n
C (^) m a (^) n G′n
W (^) ncell
C (^) m G′n
W (^) npass
= ^
The read access delay is minimized by making the widths of the transistors (Wncell and
Wnpass) as wide as possible which eliminates the last two delay terms. Of course, the
widths cannot be much larger than minimum design rule widths because the memory cells would be too large otherwise. Suppose Wncell is fixed at the largest width that will fit into
the memory cell layout without significantly increasing the memory cell area. The width of the pass transistors can be chosen to minimize the access time delay.
∂ W (^) npass
∂t (^) acc = 0
gives
W (^) npass
C (^) m C'dpass
= ---------------W (^) ncell (6)
