5.2
a. RegWrite = 0: All R-format instructions, in addition to lw, will not work because these
instructions will not be able to write their results to the register file.
b. ALUop0 = 0: beq instruction will not work because the ALU will perform addition
instead of subtraction, so the branch outcome may be wrong.
c. ALUop1 = 0: All R-format instructions.
d. Branch (or PCSrc) = 0: beq will not execute correctly. The branch instruction will
always be not taken even when it should be taken.
e. MemRead = 0: lw will not execute correctly because it will not be able to read data
from memory.
f. MemWrite = 0: sw will not work correctly because it will not be able to write to the
data memory.
5.3
a. RegWrite = 1: sw and beq should not write results to the register file. sw (beq) will
overwrite a random register with either the store address (branch target) or random data
from the memory data read port.
b. ALUop0 = 1: lw and sw will not work correctly because they will perform subtraction
instead of the addition necessary for address calculation.
c. ALUop1 = 1:lw and sw will not work correctly. Lw and sw will perform a random
operation depending on the least significant bits of the address field instead of addition
operation necessary for address calculation.
d. Branch = 1: Instructions other than branches ( beq ) will not work correctly if the ALU
Zero signal is raised. An R-format instruction that produces zero output will branch to a
random address determined by its least significant 16 bits.
e. MemRead = 1: All instructions will work correctly. (Data memory is always read, but
memory data is never written to the register file except in the case of lw.)
f. MemWrite = 1: Only sw will work correctly. The rest of instructions will store their
results in the data memory, while they should not.
5.4
Fetching, reading registers, and writing the destination register takes a total of 300ps for
both floating point add/subtract and multiply/divide. Thus, floating point add/subtract
takes 300ps + 400ps = 700ps, and floating point multiply/divide takes 300ps + 600ps =
900ps
5.6
The weighted average of the cycle times for the different instructions types is:
(600ps*0.3) + (550ps*0.15) + (400ps*0.25) + (350ps*0.10) + (200ps*0.05) +
(700ps*0.05) + (900ps*0.10) = 532.5ps.
5.8
A modification to the datapath is necessary to allow the new PC to come from a register
(Read data 1 port), and a new signal (e.g., JumpReg) to control it through a multiplexor
as shown in Figure 5.42.
A new line should be added to the truth table in Figure 5.18 on page 308 to implement
the jr instruction and a new column to produce the JumpReg signal.
